Intel 8XC196MC Benutzerhandbuch

11-10

Each EPA channel has a control register, EPAx_CON (capture/compare channels) or
COMPx_CON (compare-only channels); an event-time register, EPAx_TIME (capture/compare
channels) or COMPx_TIME (compare-only channels); and a timer input (Figure 11-5). The con-
trol register selects the timer, the mode, and either the event to be captured or the event that is to
occur. The event-time register holds the captured timer value in capture mode and the event time
in compare mode. See “Programming the Capture/Compare Channels” on page 11-18 and “Pro-
gramming the Compare-only Channels” on page 11-22 for configuration information.

In capture mode, when a valid event occurs on the pin, the value of the selected timer is captured
into a buffer. The timer value is then transferred from the buffer to the EPAx_TIME register,
which sets the EPA interrupt pending bit as shown in Figure 11-6. If enabled, an interrupt is gen-
erated. If a second event occurs before the CPU reads the first timer value in EPAx_TIME, the
current timer value is loaded into the buffer and held there. After the CPU reads the EPAx_TIME
register, the contents of the capture buffer are automatically transferred into EPAx_TIME and the
EPA interrupt pending bit is set. 

External clocking (T1CLK) with up to 6-bit prescaler

Quadrature clocking through T1CLK and T1DIR

Clock on TIMER1 overflow

TIMER1

TIMER2

EPA

Interrupt

EPA

x_CON

TGL

Reset Timer

Start A/D

††

Mode Selection

EPA Pin

EPA

x_TIME

A0807-01

Timer/Counter Unit

Capture

Buffer

Overwrite

Mode Control

Compare

EPA Capture/Compare

Channel

 x

†   

EPA0, EPA2, and EPA4.

†† 

EPA1, EPA3, and EPA5 

Bus

Internal clocking

with up to 6-bit prescaler

Reload Waveform

Generator

†