Intel 8XC196MC Benutzerhandbuch
2-5
ARCHITECTURAL OVERVIEW
The RALU uses the upper- and lower-word registers together for the 32-bit instructions and as
temporary registers for many instructions. These registers have their own shift logic and are used
for operations that require logical shifts, including normalize, multiply, and divide operations.
The six-bit loop counter counts repetitive shifts. The second-operand register stores the second
operand for two-operand instructions, including the multiplier during multiply operations and the
divisor during divide operations. During subtraction operations, the output of this register is com-
plemented before it is moved into the ALU.
temporary registers for many instructions. These registers have their own shift logic and are used
for operations that require logical shifts, including normalize, multiply, and divide operations.
The six-bit loop counter counts repetitive shifts. The second-operand register stores the second
operand for two-operand instructions, including the multiplier during multiply operations and the
divisor during divide operations. During subtraction operations, the output of this register is com-
plemented before it is moved into the ALU.
The RALU speeds up calculations by storing constants (e.g., 0, 1, and 2) in the constants register
so that they are readily available when complementing, incrementing, or decrementing bytes or
words. In addition, the constants register generates single-bit masks, based on the bit-select reg-
ister, for bit-test instructions.
so that they are readily available when complementing, incrementing, or decrementing bytes or
words. In addition, the constants register generates single-bit masks, based on the bit-select reg-
ister, for bit-test instructions.
2.3.3.1
Code Execution
The RALU performs most calculations for the microcontroller, but it does not use an accumula-
tor. Instead it operates directly on the lower register file, which essentially provides 256 accumu-
lators. Because data does not flow through a single accumulator, the microcontroller’s code
executes faster and more efficiently.
tor. Instead it operates directly on the lower register file, which essentially provides 256 accumu-
lators. Because data does not flow through a single accumulator, the microcontroller’s code
executes faster and more efficiently.
2.3.3.2
Instruction Format
MCS 96 microcontrollers combine a large set of general-purpose registers with a three-operand
instruction format. This format allows a single instruction to specify two source registers and a
separate destination register. For example, the following instruction multiplies two 16-bit vari-
ables and stores the 32-bit result in a third variable.
instruction format. This format allows a single instruction to specify two source registers and a
separate destination register. For example, the following instruction multiplies two 16-bit vari-
ables and stores the 32-bit result in a third variable.
MUL
RESULT, FACTOR_1, FACTOR_2
;multiply FACTOR_1 and FACTOR_2
;and store answer in RESULT
;(RESULT)
;and store answer in RESULT
;(RESULT)
←
(FACTOR_1 × FACTOR_2)
An 80C186 microprocessor requires four instructions to accomplish the same operation. The fol-
lowing example shows the equivalent code for an 80C186 microprocessor.
lowing example shows the equivalent code for an 80C186 microprocessor.
MOV
AX, FACTOR_1
;move FACTOR_1 into accumulator (AX)
;(AX)
;(AX)
←
FACTOR1
MUL
FACTOR_2
;multiply FACTOR_2 and AX
;(DX:AX)
;(DX:AX)
←
(AX)×(FACTOR_2)
MOV
RESULT, AX
;move lower byte into RESULT
;(RESULT)
;(RESULT)
←
(AX)
MOV
RESULT+2, DX
;move upper byte into RESULT+2
;(RESULT+2)
;(RESULT+2)
←
(DX)