Intel 8XC196MC Benutzerhandbuch
8XC196MC, MD, MH USER’S MANUAL
3-6
3.2.1
Direct Addressing
Direct addressing directly accesses a location in the 256-byte lower register file, without involv-
ing the memory controller. Windowing allows you to remap other sections of memory into the
lower register file for direct access (see Chapter 4, “Memory Partitions,” for details). You specify
the registers as operands within the instruction. The register addresses must conform to the align-
ment rules for the operand type. Depending on the instruction, up to three registers can take part
in a calculation. The following instructions use direct addressing:
ing the memory controller. Windowing allows you to remap other sections of memory into the
lower register file for direct access (see Chapter 4, “Memory Partitions,” for details). You specify
the registers as operands within the instruction. The register addresses must conform to the align-
ment rules for the operand type. Depending on the instruction, up to three registers can take part
in a calculation. The following instructions use direct addressing:
ADD
AX,BX,CX ;
AX
←
BX + CX
ADDB AL,BL,CL
; AL
←
BL + CL
MULB AX,BL ;
AX
←
AX
×
BL
INCB CL
; CL
←
CL + 1
3.2.2
Immediate Addressing
Immediate addressing mode accepts one immediate value as an operand in the instruction. You
specify an immediate value by preceding it with a number symbol (#). An instruction can contain
only one immediate value; the remaining operands must be direct references. The following in-
structions use immediate addressing:
specify an immediate value by preceding it with a number symbol (#). An instruction can contain
only one immediate value; the remaining operands must be direct references. The following in-
structions use immediate addressing:
ADD
AX,#340
; AX
←
AX + 340
PUSH #1234H
; SP
←
SP - 2
; MEM_WORD(SP)
←
1234H
DIVB AX,#10
; AL
←
AX/10
; AH
←
AX MOD 10
3.2.3
Indirect Addressing
The indirect addressing mode accesses an operand by obtaining its address from a WORD regis-
ter in the lower register file. You specify the register containing the indirect address by enclosing
it in square brackets ([ ]). The indirect address can refer to any location within the address space,
including the register file. The register that contains the indirect address must be word-aligned,
and the indirect address must conform to the rules for the operand type. An instruction can contain
only one indirect reference; any remaining operands must be direct references. The following in-
structions use indirect addressing:
ter in the lower register file. You specify the register containing the indirect address by enclosing
it in square brackets ([ ]). The indirect address can refer to any location within the address space,
including the register file. The register that contains the indirect address must be word-aligned,
and the indirect address must conform to the rules for the operand type. An instruction can contain
only one indirect reference; any remaining operands must be direct references. The following in-
structions use indirect addressing:
LD
AX,[BX]
; AX
←
MEM_WORD(BX)
Table 3-3. Definition of Temporary Registers
Temporary Register
Description
AX
word-aligned 16-bit register; AH is the high byte of AX and AL is the low byte
BX
word-aligned 16-bit register; BH is the high byte of BX and BL is the low byte
CX
word-aligned 16-bit register; CH is the high byte of CX and CL is the low byte
DX
word-aligned 16-bit register; DH is the high byte of DX and DL is the low byte