Renesas R5S72641 Benutzerhandbuch
Section 2 CPU
R01UH0134EJ0400 Rev. 4.00
Page 81 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
Instruction
Instruction Code
Operation
Execu-
tion
Cycles
T Bit
Compatibility
SH2,
SH2E SH4 SH-2A
EXTU.B Rm,Rn
0110nnnnmmmm1100
Byte in Rm is
zero-extended
Rn
1
Yes
Yes
Yes
EXTU.W Rm,Rn
0110nnnnmmmm1101
Word in Rm is
zero-extended
Rn
1
Yes
Yes
Yes
MAC.L @Rm+,@Rn+ 0000nnnnmmmm1111 Signed operation of (Rn)
(Rm) + MAC
MAC
32
32 + 64 64 bits
4
Yes
Yes
Yes
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of (Rn)
(Rm) + MAC
MAC
16
16 + 64 64 bits
3
Yes
Yes
Yes
MUL.L Rm,Rn
0000nnnnmmmm0111
Rn
Rm MACL
32
32 32 bits
2
Yes
Yes
Yes
MULR R0,Rn
0100nnnn10000000
R0
Rn Rn
32
32 32 bits
2
Yes
MULS.W Rm,Rn
0010nnnnmmmm1111
Signed operation of Rn
Rm
MACL
16
16 32 bits
1
Yes
Yes
Yes
MULU.W Rm,Rn
0010nnnnmmmm1110
Unsigned operation of Rn
Rm
MACL
16
16 32 bits
1
Yes
Yes
Yes
NEG Rm,Rn
0110nnnnmmmm1011
0-Rm
Rn
1
Yes
Yes
Yes
NEGC Rm,Rn
0110nnnnmmmm1010
0-Rm-T
Rn, borrow T
1
Borrow Yes
Yes Yes
SUB Rm,Rn
0011nnnnmmmm1000
Rn-Rm
Rn
1
Yes
Yes
Yes
SUBC Rm,Rn
0011nnnnmmmm1010
Rn-Rm-T
Rn, borrow T
1
Borrow Yes
Yes Yes
SUBV Rm,Rn
0011nnnnmmmm1011
Rn-Rm
Rn, underflow T
1
Over-
flow
Yes Yes
Yes