Renesas R5S72641 Benutzerhandbuch
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Section 17 I
2
C Bus Interface 3
R01UH0134EJ0400 Rev. 4.00
Page 875 of 2108
Sep 24, 2014
SH7262 Group, SH7264 Group
TDRE
TEND
ICDRS
ICDRR
1
9
2
3
4
5
6
7
8
9
TRS
ICDRT
A
A
Data n
SCL
(Master output)
SDA
(Master output)
SDA
(Slave output)
SCL
(Slave output)
Bit 7
Slave transmit mode
Slave receive
mode
mode
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
[3] Clear TEND
[5] Clear TDRE
[4] Read ICDRR (dummy read)
after clearing TRS
after clearing TRS
User
processing
Figure 17.10 Slave Transmit Mode Operation Timing (2)