Intel Gigabit Ethernet Controllers Benutzerhandbuch

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The EEPROM interface trace routing is not critical because the interface runs at a very slow speed.

Note: For the 82544GC/EI, 82540EP/EM, 82541xx, and 82547GI/EI, the EEPROM access algorithm 

drives extra pulses on the shift clock at the beginnings and ends of read and write cycles. the extra 

pulses might violate the timing specifications of some EEPROM devices. In selecting a serial 

EEPROM, choose a device that specifies “don’t care” shift clock states between accesses.

The Ethernet controller provides two different methods for software access to the EEPROM. 

Software can either use the built-in controller to read the EEPROM, or access the EEPROM 
directly using the EEPROM’s 4-wire interface.

Software can use the EEPROM Read register (EERD) to cause the Ethernet controller to read a 

word from the EEPROM that the software can then use. To do this, software writes the address to 

read the Read Address (EERD.ADDR) field and then simultaneously writes a 1b to the Start Read 
bit (EERD.START). The Ethernet controller then reads the word from the EEPROM, sets the Read 

Done bit (EERD.DONE), and puts the data in the Read Data field (EERD.DATA). Software can 

poll the EEPROM Read register until it sees the EERD.DONE bit set, then use the data from the 
EERD.DATA field. Any words read this way are not written to hardware’s internal registers.

Software can also directly access the EEPROM’s 4-wire interface through the EEPROM/FLASH 

Control Register (EEC). It can use this for reads, writes, or other EEPROM operations.

To directly access the EEPROM, software should follow these steps:

1. Write a 1b to the EEPROM Request bit (EEC.EE_REQ).

2. Read the EEPROM Grant bit (EEC.EE_GNT) until it becomes 1b. It remains 0b as long as the 

hardware is accessing the EEPROM.

3. Write or read the EEPROM using the direct access to the 4-wire interface as defined in the 

EEPROM/FLASH Control & Data Register (EEC). The exact protocol used depends on the 

EEPROM placed on the board and can be found in the appropriate data sheet.

4. Write a 0b to the EEPROM Request bit (EEC.EE_REQ).

Software can cause the Ethernet controller to re-read the hardware accessed fields of the EEPROM 

(setting hardware’s internal registers appropriately) by writing a 1b to the EEPROM Reset bit of 

the Extended Device Control Register (CTRL_EXT.EE_RST). This action will also cause a reset.

The Ethernet controller uses the Signature and CRC fields to determine if an EEPROM is present 

by attempting to read the EEPROM. The Ethernet controller first reads the Initialization Control 

Word 1 at address 0Ah and then checks the received value for bits 15 and 14. If bit 15 is 0b and bit 
14 is 1b, the Ethernet controller considers the EEPROM to be present and valid. It then reads the 

additional EEPROM words and programs its internal registers based on the values read. Otherwise, 

it ignores the values it read from the Initialization Control Word 1 and does not read any other 
words.