Intel Gigabit Ethernet Controllers Benutzerhandbuch

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The Ethernet controller supports back-to-back transmit Inter-Frame-Spacing (IFS) of 960 ns in 100 

Mb/s operation and 9.6 

µs in 10 Mb/s operation. Although back-to-back transmission is normally 

desirable, sometimes it can actually hurt performance in half-duplex environments due to excessive 

collisions. Excessive collisions are likely to occur in environments where one station is attempting 

to send large frames back-to-back, while another station is attempting to send acknowledge (ACK) 
packets.

The Ethernet controller contains an Adaptive IFS Throttle - AIT register (see 

) that 

enables the implementation of a driver-based adaptive IFS algorithm for collision reduction. 

Adaptive IFS throttles back-to-back transmissions in the transmit MAC and delays their transfer to 
the CSMA/CD transmit function. Normally, this register should be set to zero. However, if 

additional delay is desired between back-to-back transmits, then this register can be set with a 

value greater than zero. By setting this register with a higher value, collisions can be reduced in 
certain half-duplex environments, because the adapter is less aggressive in acquiring the wire, and 

therefore less likely to collide with another adapter that attempts to transmit after minimum IFS.

IFS and IPG (inter-packet gap) are equivalent terms and may be used interchangeably in this 

manual.

The AIFS field provides a similar function to the IGPT field in the TIPG register (see 

). However this Adaptive IFS throttle register counts in units of transmit clocks (which are 

8 ns, 80 ns, 800 ns for 10, 100, 1000 Mb/s mode respectively), and is 16 bits wide, thus providing a 

greater maximum delay value.

Using values lower than a certain minimum (determined by the ratio of transmit clock to link 
speed), has no effect on back-to-back transmission. This is because the Ethernet controller does not 

start transmission until the minimum IEEE IFS (9.6 us at 10 Mb, 960 ns at 100 Mb, and 96 ns at 1 

Gb) has been met regardless of the value of Adaptive IFS. For example, if the Ethernet controller is 
configured for 100 Mb/s operation, the minimum IEEE IFS at 100 Mb/s is 960 ns. Setting AIFS to 

a value of 10 (decimal) would not affect back-to-back transmission time on the wire, because the 
800 ns delay introduced (10 * 80n s = 800 ns) is less than the minimum IEEE IFS delay of 960 ns. 

However, setting this register with a value of 20 (decimal), which corresponds to 1600 ns for the 

above example, would delay back-to-back transmits because the ensuing 1600 ns delay is greater 
than the minimum IFS time of 960 ns.

It is important to note that this register has no effect on transmissions that occur immediately after 

receives or on transmissions that are not back-to-back (unlike the IPGR1 and IPGR2 values in the 

TIPG register described in 

). In addition, Adaptive IFS also has no effect on re-

transmission timing (re-transmissions occur after collisions). Therefore, AIFS is only enabled in 

back-to-back transmission. The AIFS value is NOT additive to the TIPG.IPGT value; instead, the 

actual IPG equals the larger of AIFS and TIPG.IPGT.

1.

Not applicable to the 82541xx or 82547GI/EI.