Texas Instruments SM320F2812-HT Benutzerhandbuch
Analog Input on
Channel Ax
Analog Input on
Channel Bv
ADC Clock
Sample and Hold
SH Pulse
t
SH
t
dschA0_n
t
dschB0_n
t
dschB0_n+1
Sample n
Sample n+1
Sample n+2
t
dschA0_n+1
t
d(SH)
ADC Event Trigger from
EV or Other Sources
SMODE Bit
SGUS062A – JUNE 2009 – REVISED APRIL 2010
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6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1)
In simultaneous mode, the ADC can continuously convert input signals on any one pair of channels
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB),
software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC does conversions on
two selected channels on every Sample/Hold pulse. The conversion time and latency of the Result
register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the
Result register update. The selected channels are sampled simultaneously at the falling edge of the
Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum)
or 16 ADC clocks wide (maximum).
(A0/B0 to A7/B7). The ADC can start conversions on event triggers from the Event Managers (EVA/EVB),
software trigger, or from an external ADCSOC signal. If the SMODE bit is 1, the ADC does conversions on
two selected channels on every Sample/Hold pulse. The conversion time and latency of the Result
register update are explained below. The ADC interrupt flags are set a few SYSCLKOUT cycles after the
Result register update. The selected channels are sampled simultaneously at the falling edge of the
Sample/Hold pulse. The Sample/Hold pulse width can be programmed to be 1 ADC clock wide (minimum)
or 16 ADC clocks wide (maximum).
NOTE
In Simultaneous mode, the ADCIN channel pair select has to be A0/B0, A1/B1, ..., A7/B7,
and not in other combinations (such as A1/B3, etc.).
and not in other combinations (such as A1/B3, etc.).
Figure 6-40. Simultaneous Sampling Mode Timing
Table 6-51. Simultaneous Sampling Mode Timing
(1)
AT 25-MHz ADC
SAMPLE n
SAMPLE n + 1
CLOCK,
REMARKS
t
c(ADCCLK)
= 40 ns
Delay time from event
t
d(SH)
2.5t
c(ADCCLK)
trigger to sampling
Sample/Hold
(1 + Acqps) ×
Acqps value = 0–15
t
SH
40 ns with Acqps = 0
width/Acquisition Width
t
c(ADCCLK)
ADCTRL1[8:11]
Delay time for first result
t
d(schA0_n)
to appear in Result
4t
c(ADCCLK)
160 ns
register
Delay time for first result
t
d(schB0_n)
to appear in Result
5t
c(ADCCLK)
200 ns
register
Delay time for successive
(3 + Acqps) ×
t
d(schA0_n+1)
results to appear in Result
120 ns
t
c(ADCCLK)
register
(1)
Not production tested.
140
Electrical Specifications
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