Freescale Semiconductor MCF52211 Benutzerhandbuch
DMA Controller Module
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
17-10
Freescale Semiconductor
15–12
SMOD
Source address modulo. Defines the size of the source data circular buffer used by the DMA Controller. If enabled
(SMOD is non-zero), the buffer base address is located on a boundary of the buffer size. The value of this
boundary is based upon the initial source address (SAR). The base address should be aligned to a 0-modulo-
circular buffer size boundary. Misaligned buffers are not possible. The boundary is forced to the value determined
by the upper address bits in the field selection.
(SMOD is non-zero), the buffer base address is located on a boundary of the buffer size. The value of this
boundary is based upon the initial source address (SAR). The base address should be aligned to a 0-modulo-
circular buffer size boundary. Misaligned buffers are not possible. The boundary is forced to the value determined
by the upper address bits in the field selection.
11–8
DMOD
Destination address modulo. Defines the size of the destination data circular buffer used by the DMA Controller.
If enabled (DMOD value is non-zero), the buffer base address is located on a boundary of the buffer size. The
value of this boundary depends on the initial destination address (DAR). The base address should be aligned to
a 0-modulo- circular buffer size boundary. Misaligned buffers are not possible. The boundary is forced to the value
determined by the upper address bits in the field selection.
If enabled (DMOD value is non-zero), the buffer base address is located on a boundary of the buffer size. The
value of this boundary depends on the initial destination address (DAR). The base address should be aligned to
a 0-modulo- circular buffer size boundary. Misaligned buffers are not possible. The boundary is forced to the value
determined by the upper address bits in the field selection.
.
7
D_REQ
Disable request. DMA hardware automatically clears the corresponding DCRn[EEXT] bit when the byte count
register reaches zero.
register reaches zero.
0 EEXT bit is not affected.
1 EEXT bit is cleared when the BCR is exhausted.
1 EEXT bit is cleared when the BCR is exhausted.
6
Reserved; should be cleared.
Table 17-4. DCRn Field Descriptions (continued)
Field
Description
SMOD
Circular Buffer Size
0000
Buffer Disabled
0001
16 Bytes
0010
32 Bytes
...
...
1111
256 Kbytes
SMOD
Circular Buffer Size
0000
Buffer Disabled
0001
16 Bytes
0010
32 Bytes
...
...
1111
256 Kbytes
DMOD
Circular Buffer Size
0000
Buffer Disabled
0001
16 Bytes
0010
32 Bytes
...
...
1111
256 Kbytes