Freescale Semiconductor MCF52211 Benutzerhandbuch
General Purpose Timer Module (GPT)
MCF52211 ColdFire® Integrated Microcontroller Reference Manual, Rev. 2
21-4
Freescale Semiconductor
21.5.3
SYNCn
The SYNCn pin is for synchronization of the timer counter. It can be used to synchronize the counter with
externally-timed or clocked events. A high signal on this pin clears the counter.
externally-timed or clocked events. A high signal on this pin clears the counter.
21.6
Memory Map and Registers
shows the memory map of the GPT module. The base address for GPT is IPSBAR +
0x1A_0000.
NOTE
Reading reserved or unimplemented locations returns zeros. Writing to
reserved or unimplemented locations has no effect.
reserved or unimplemented locations has no effect.
Table 21-3. GPT Memory Map
IPSBAR
Offset
1
Register
Width
(bits)
Access
Reset Value
Section/Page
Supervisor Mode Access Only
0x1A_0000
GPT IC/OC Select Register (GPTIOS)
8
R/W
0x00
0x1A_0001
GPT Compare Force Register (GPTCFORC)
8
R/W
0x00
0x1A_0002
GPT Output Compare 3 Mask Register (GPTOC3M)
8
R/W
0x00
0x1A_0003
GPT Output Compare 3 Data Register (GPTOC3D)
8
R/W
0x00
0x1A_0004
GPT Counter Register High (GPTCNTH)
2
8
R
0x00
0x1A_0005
GPT Counter Register Low (GPTCNTL)
2
8
R
0x00
0x1A_0006
GPT System Control Register 1 (GPTSCR1)
8
R/W
0x00
0x1A_0008
GPT Toggle-on-Overflow Register (GPTTOV)
8
R/W
0x00
0x1A_0009
GPT Control Register 1 (GPTCTL1)
8
R/W
0x00
0x1A_000B
GPT Control Register 2 (GPTCTL2)
8
R/W
0x00
0x1A_000C
GPT Interrupt Enable Register (GPTIE)
8
R/W
0x00
0x1A_000D
GPT System Control Register 2 (GPTSCR2)
8
R/W
0x00
0x1A_000E
GPT Flag Register 1 (GPTFLG1)
8
R/W
0x00
0x1A_000F
GPT Flag Register 2 (GPTFLG2)
8
R/W
0x00
0x1A_0010
GPT Channel 0 Register High (GPTC0H)
8
0x1A_0011
GPT Channel 0 Register Low (GPTC0L)
8
0x1A_0012
GPT Channel 1 Register High (GPTC1H)
8
0x1A_0013
GPT Channel 1 Register Low (GPTC1L)
8
0x1A_0014
GPT Channel 2 Register High (GPTC2H)
8
0x1A_0015
GPT Channel 2 Register Low (GPTC2L)
8
0x1A_0016
GPT Channel 3 Register High (GPTC3H)
8