Motorola IH5 Benutzerhandbuch
Block Diagram
http://www.motorola.com/computer/literature
6-15
6
Raven Watchdog Timers
The Raven ASIC contains two Watchdog timers, WDT1 and WDT2. Each
timer is functionally equivalent but independent. These timers will
continuously decrement until they reach a count of 0 or are reloaded by
software. The timeout period is programmable from 1 microsecond up to
1024 milliseconds. There is an additional 4.8 second delay for each timer
output provided by an external PLD. If the timer count reaches 0, a timer
output signal will be asserted. The output of Watchdog Timer 1 an MPIC
interrupt. The output of Watchdog Timer 2 is logically ORed onboard to
provide a hard reset.
timer is functionally equivalent but independent. These timers will
continuously decrement until they reach a count of 0 or are reloaded by
software. The timeout period is programmable from 1 microsecond up to
1024 milliseconds. There is an additional 4.8 second delay for each timer
output provided by an external PLD. If the timer count reaches 0, a timer
output signal will be asserted. The output of Watchdog Timer 1 an MPIC
interrupt. The output of Watchdog Timer 2 is logically ORed onboard to
provide a hard reset.
Following a device reset, WDT1 is enabled with a default timeout of 512
milliseconds and WDT2 is enabled with a default timeout of 576
milliseconds. Each of these signals is typically delayed an additional 4.8
seconds (2 seconds minimum) using logic external to Raven. Each timer
must be disabled or reloaded by software to prevent a timeout. Software
may reload a new timer value or force the timer to reload a previously
loaded value. To disable or load/reload a timer requires a two step process.
The first step is to write the pattern $55 to the timer register key field which
will arm the timer register to enable an update. The second step is to write
the pattern $AA to the key field along with the new timer information.
During the power-up configuration of the Raven ASIC, PPCBug disables
the two Watchdog timers.
milliseconds and WDT2 is enabled with a default timeout of 576
milliseconds. Each of these signals is typically delayed an additional 4.8
seconds (2 seconds minimum) using logic external to Raven. Each timer
must be disabled or reloaded by software to prevent a timeout. Software
may reload a new timer value or force the timer to reload a previously
loaded value. To disable or load/reload a timer requires a two step process.
The first step is to write the pattern $55 to the timer register key field which
will arm the timer register to enable an update. The second step is to write
the pattern $AA to the key field along with the new timer information.
During the power-up configuration of the Raven ASIC, PPCBug disables
the two Watchdog timers.
M48T559 Watchdog Timer
The M48T559 contains one Watchdog timer. The reset output of the
Watchdog timer is logically ORed into the reset logic and will generate a
hard reset if the reset output is enabled and the timer expires. If the
interrupt output is enabled, the Watchdog timer will generate an RTC
interrupt if the timer expires. Refer to the device data sheet and the
MCPN750A CompactPCI Single Board Computer Programmer’s
Reference Guide (MCPN750A/PG) for programming information.
Watchdog timer is logically ORed into the reset logic and will generate a
hard reset if the reset output is enabled and the timer expires. If the
interrupt output is enabled, the Watchdog timer will generate an RTC
interrupt if the timer expires. Refer to the device data sheet and the
MCPN750A CompactPCI Single Board Computer Programmer’s
Reference Guide (MCPN750A/PG) for programming information.