Intel 8XC196MD Benutzerhandbuch
5-35
STANDARD AND PTS INTERRUPTS
5.6.5.1
A/D Scan Mode Cycles
Software must start the first A/D conversion. After the A/D conversion complete interrupt ini-
tiates the PTS routine, the following actions occur.
tiates the PTS routine, the following actions occur.
1.
The PTS reads the first command (from address XXXX), stores it in a temporary location,
and increments the PTSPTR1 register twice. PTSPTR1 now points to the first blank
location in the command/data table (address XXXX + 2).
and increments the PTSPTR1 register twice. PTSPTR1 now points to the first blank
location in the command/data table (address XXXX + 2).
2.
The PTS reads the AD_RESULT register, stores the results of the first conversion into
location XXXX + 2 in the command/data table, and increments the PTSPTR1 register
twice. PTSPTR1 now points to XXXX + 4.
location XXXX + 2 in the command/data table, and increments the PTSPTR1 register
twice. PTSPTR1 now points to XXXX + 4.
3.
The PTS loads the command from the temporary location into the AD_COMMAND
register. This completes the first A/D scan cycle and initiates the next A/D conversion.
register. This completes the first A/D scan cycle and initiates the next A/D conversion.
4.
If UPDT (PTSCON.3) is clear, the original address is reloaded into the PTSPTR1 register.
The next cycle uses the same command and overwrites previous data. If UPDT is set, the
updated address remains in PTSPTR1 and the next cycle uses a new command and stores
the conversion results at the new address.
The next cycle uses the same command and overwrites previous data. If UPDT is set, the
updated address remains in PTSPTR1 and the next cycle uses a new command and stores
the conversion results at the new address.
5.
PTSCOUNT is decremented and the CPU returns to regular program execution. When the
next A/D conversion complete interrupt occurs, the cycle repeats. When PTSCOUNT
reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit,
which requests the end-of-PTS interrupt.
next A/D conversion complete interrupt occurs, the cycle repeats. When PTSCOUNT
reaches zero, hardware clears the corresponding PTSSEL bit and sets the PTSSRV bit,
which requests the end-of-PTS interrupt.
5.6.5.2
A/D Scan Mode Example 1
The command/data table shown in Table 5-8 sets up a series of A/D conversions, beginning with
channel 7 and ending with channel 4. Each table entry is a word (two bytes). Table 5-9 shows the
corresponding PTSCB.
channel 7 and ending with channel 4. Each table entry is a word (two bytes). Table 5-9 shows the
corresponding PTSCB.
Software starts a conversion on channel 7. Upon completion of the conversion, the A/D conver-
sion complete interrupt initiates the A/D scan mode routine. Step 1 stores the channel 6 command
in a temporary location and increments PTSPTR1 to 3002H. Step 2 stores the result of the channel
7 conversion in location 3002H and increments PTSPTR1 to 3004H. Step 3 loads the channel 6
command from the temporary location into the AD_COMMAND register to start the next con-
sion complete interrupt initiates the A/D scan mode routine. Step 1 stores the channel 6 command
in a temporary location and increments PTSPTR1 to 3002H. Step 2 stores the result of the channel
7 conversion in location 3002H and increments PTSPTR1 to 3004H. Step 3 loads the channel 6
command from the temporary location into the AD_COMMAND register to start the next con-