Intel 8XC196MD Benutzerhandbuch
8XC196MC, MD, MH USER’S MANUAL
A-2
Table A-1. Opcode Map (Left Half)
Opcode
x
0
x
1
x
2
x
3
x
4
x
5
x
6
x
7
0
x
SKIP
CLR
NOT
NEG
XCH
di
DEC
EXT
INC
1
x
CLRB
NOTB
NEGB
XCHB
di
DECB
EXTB
INCB
2
x
SJMP
3
x
JBC
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
4
x
AND 3op
ADD 3op
di
im
in
ix
di
im
in
ix
5
x
ANDB 3op
ADDB 3op
di
im
in
ix
di
im
in
ix
6
x
AND 2op
ADD 2op
di
im
in
ix
di
im
in
ix
7
x
ANDB 2op
ADDB 2op
di
im
in
ix
di
im
in
ix
8
x
OR
XOR
di
im
in
ix
di
im
in
ix
9
x
ORB
XORB
di
im
in
ix
di
im
in
ix
A
x
LD
ADDC
di
im
in
ix
di
im
in
ix
B
x
LDB
ADDCB
di
im
in
ix
di
im
in
ix
C
x
ST
BMOV
ST
STB
CMPL
STB
di
in
ix
di
in
ix
D
x
JNST
JNH
JGT
JNC
JNVT
JNV
JGE
JNE
Ex
DJNZ
DJNZW
TIJMP
BR
in
LJMP
Fx
RET
PUSHF
POPF
PUSHA
POPA
IDLPD
TRAP
NOTE:
The first digit of the opcode is listed vertically, and the second digit is listed horizontally. The
related instruction mnemonic is shown at the intersection of the two digits. Shading indicates
reserved opcodes. If the CPU attempts to execute an unimplemented opcode, an interrupt
occurs. For more information, see “Unimplemented Opcode” on page 5-6.
related instruction mnemonic is shown at the intersection of the two digits. Shading indicates
reserved opcodes. If the CPU attempts to execute an unimplemented opcode, an interrupt
occurs. For more information, see “Unimplemented Opcode” on page 5-6.