Intel 8XC196MH Benutzerhandbuch
11-3
EVENT PROCESSOR ARRAY (EPA)
P2.4
P2.5
P2.6
P2.7
P2.5
P2.6
P2.7
—
—
—
P2.4
P2.5
P2.6
P2.7
P7.2
P7.3
P2.5
P2.6
P2.7
P7.2
P7.3
P2.4
P2.5
P2.6
P2.3
P2.5
P2.6
P2.3
—
—
—
COMP0
COMP1
COMP2
COMP3
COMP4
COMP5
COMP1
COMP2
COMP3
COMP4
COMP5
O
Output of the compare-only channels.
Table 11-3. EPA Control and Status Registers
Mnemonic
Address
Description
MC
MD
MH
COMP0_CON
COMP1_CON
COMP2_CON
COMP3_CON
COMP4_CON
COMP5_CON
COMP1_CON
COMP2_CON
COMP3_CON
COMP4_CON
COMP5_CON
1F58H
1F5CH
1F60H
1F64H
1F64H
—
—
—
1F58H
1F5CH
1F60H
1F64H
1F68H
1F64H
1F68H
1F6CH
1F58H
1F5CH
1F60H
1F4CH
—
—
—
EPA
x
Compare Control
These registers control the functions of the
compare-only channels.
compare-only channels.
COMP0_TIME
COMP1_TIME
COMP2_TIME
COMP3_TIME
COMP4_TIME
COMP5_TIME
COMP1_TIME
COMP2_TIME
COMP3_TIME
COMP4_TIME
COMP5_TIME
1F5AH
1F5EH
1F62H
1F66H
1F5EH
1F62H
1F66H
—
—
—
1F5AH
1F5EH
1F5EH
1F62H
1F66H
1F66H
1F6AH
1F6EH
1F6EH
1F5AH
1F5EH
1F62H
1F4EH
1F5EH
1F62H
1F4EH
—
—
—
EPA
x
Compare Time
These registers contain the time at which an event
is to occur on the compare-only channels.
is to occur on the compare-only channels.
EPA0_CON
EPA1_CON
EPA2_CON
EPA3_CON
EPA4_CON
EPA5_CON
EPA1_CON
EPA2_CON
EPA3_CON
EPA4_CON
EPA5_CON
1F40H
1F44H
1F48H
1F44H
1F48H
1F4CH
—
—
—
1F40H
1F44H
1F48H
1F44H
1F48H
1F4CH
1F50H
1F54H
1F54H
1F40H
1F44H
1F44H
—
—
—
—
—
—
—
EPA
x
Capture/Compare
Control
These registers control the functions of the
capture/compare channels. EPA1_CON and
EPA3_CON require an extra byte because they
contain an additional bit for PWM remap mode.
These two registers must be addressed as words;
the others can be addressed as bytes.
capture/compare channels. EPA1_CON and
EPA3_CON require an extra byte because they
contain an additional bit for PWM remap mode.
These two registers must be addressed as words;
the others can be addressed as bytes.
EPA0_TIME
EPA1_TIME
EPA2_TIME
EPA3_TIME
EPA4_TIME
EPA5_TIME
EPA1_TIME
EPA2_TIME
EPA3_TIME
EPA4_TIME
EPA5_TIME
1F42H
1F46H
1F4AH
1F4EH
1F46H
1F4AH
1F4EH
—
—
—
1F42H
1F46H
1F46H
1F4AH
1F4EH
1F4EH
1F52H
1F56H
1F56H
1F42H
1F46H
1F46H
—
—
—
—
—
—
—
EPA
x
Capture/Compare Time
In capture mode, these registers contain the
captured timer value. In compare mode, these
registers contain the time at which an event is to
occur. In capture mode, these registers are
buffered to allow two captures before an overrun
occurs. However, they are not buffered in compare
mode.
captured timer value. In compare mode, these
registers contain the time at which an event is to
occur. In capture mode, these registers are
buffered to allow two captures before an overrun
occurs. However, they are not buffered in compare
mode.
INT_MASK
0008H
0008H
0008H
Interrupt Mask
The bits in this 8-bit register enable and disable
(mask) the interrupts associated with the corre-
sponding bits in the INT_PEND register.
(mask) the interrupts associated with the corre-
sponding bits in the INT_PEND register.
INT_MASK1
0013H
0013H
0013H
Interrupt Mask 1
The bits in this 8-bit register enable and disable
(mask) the interrupts associated with the corre-
sponding bits in the INT_PEND1 register.
(mask) the interrupts associated with the corre-
sponding bits in the INT_PEND1 register.
Table 11-2. EPA and Timer/Counter Signals (Continued)
Port Pin
EPA
Signals
EPA
Signal
Type
Description
8XC196MC
8XC196MD
8XC196MH