Benutzerhandbuch für AMD Am188TMER

Inhaltsverzeichnis

• Help Questions

  3
  • Customer Service

    3
  • Hotline/World Wide Web Support

    3
  • Documentation and Literature

    3
• Table of Contents

  5
  • List of Figures

    9
  • List of Tables

    11
• Introduction and Overview

  13
  • Design Philosophy

    13
  • Purpose of this Manual

    13
  • Intended Audience

    13
  • User’s Manual Overview

    13
  • AMD Documentation

    14
• Chap 1:Features and Performance

  15
  • 1.1 Key Features and Benefits

    15
  • 1.2 Distinctive Characteristics

    16
  • Figure 1-1 Am186ER Microcontroller Block Diagram

    18
  • Figure 1-2 Am188ER Microcontroller Block Diagram

    19
  • 1.3 Application Considerations

    20
  • Figure 1-3 Basic Functional System Design

    20
  • 1.3.1 Clock Generation

    20
  • 1.3.2 Memory Interface

    21
  • 1.3.3 Serial Communications Port

    21
  • 1.4 Third-Party Development Support Products

    22
• Chap 2:Programming

  23
  • 2.1 Register Set

    23
  • Figure 2-1 Register Set

    24
  • 2.1.1 Processor Status Flags Register

    24
  • Figure 2-2 Processor Status Flags Register (FLAGS)

    24
  • 2.2 Memory Organization and Address Generation

    25
  • Figure 2-3 Physical Address Generation

    26
  • 2.3 I/O Space

    26
  • Figure 2-4 Memory and I/O Space

    26
  • 2.4 Instruction Set

    26
  • Table 2-1 Instruction Set

    27
  • 2.5 Segments

    30
  • Table 2-2 Segment Register Selection Rules

    30
  • 2.6 Data Types

    30
  • Figure 2-5 Supported Data Types

    31
  • 2.7 Addressing Modes

    32
  • Register and Immediate Operands

    32
  • Memory Operands

    32
  • Table 2-3 Memory Addressing Mode Examples

    32
• Chap 3:System Overview

  33
  • 3.1 Pin Descriptions

    33
    • A19–A0

      33
    • AD7–AD0

      33
    • AD15–AD8

      34
    • AO15–AO8

      34
    • CLKOUTB

      36
    • DEN

      36
    • DRQ1–DRQ0

      36
    • ALE

      34
    • ARDY

      35
    • BHE/ADEN

      35
    • CLKOUTA

      36
    • DT/R

      36
    • GND

      36
    • HLDA

      36
    • HOLD

      37
    • INT0

      37
    • INT1/SELECT

      37
    • INT2/INTA0

      38
    • INT3/INTA1/IRQ

      38
    • INT4

      38
    • LCS/ONCE0

      39
    • MCS3/RFSH

      39
    • MCS2–MCS0

      39
    • NMI

      39
    • PCS3–PCS0

      40
    • PCS5/A1

      40
    • PCS6/A2

      40
    • PIO31–PIO0

      41
    • Table 3-1 PIO Pin Assignments—Numeric Listing

      42
    • Table 3-2 PIO Pin Assignments—Alphabetic Listing

      43
    • RD

      44
    • RES

      44
    • RFSH2/ADEN

      44
    • RXD

      44
    • S2

      45
    • S1/IMDIS

      45
    • S0/SREN

      45
    • Table 3-3 Bus Cycle Encoding

      45
    • S6/CLKSEL1

      45
    • SCLK

      46
    • SDATA

      46
    • SDEN1–SDEN0

      46
    • SRDY

      46
    • TMRIN0

      46
    • TMRIN1

      47
    • TMROUT0

      47
    • TMROUT1

      47
    • TXD

      47
    • UCS/ONCE1

      47
    • UZI/CLKSEL2

      47
    • Table 3-4 Clocking Modes

      48
    • VCC

      48
    • WHB

      48
    • WLB/WB

      48
    • WR

      49
    • X1

      49
    • X2

      49
  • 3.1.1 Pins That Are Used by Emulators

    49
  • 3.2 Bus Operation

    50
    • Figure 3-1 Am186ER Microcontroller Address Bus—Nor...

      51
    • Figure 3-2 Am186ER Microcontroller—Read and Write ...

      51
    • Figure 3-3 Am188ER Microcontroller Address Bus—Nor...

      52
    • Figure 3-4 Am188ER Microcontroller—Read and Write ...

      52
  • 3.3 Bus Interface Unit

    53
    • 3.3.1 Nonmultiplexed Address Bus

      53
    • 3.3.2 Byte Write Enables

      53
    • 3.3.3 Pseudo Static RAM (PSRAM) Support

      53
  • 3.4 Clock and Power Management Unit

    55
    • 3.4.1 Phase-Locked Loop (PLL)

      55
    • Table 3-5 Maximum and Minimum Clock Frequencies

      55
    • 3.4.2 Crystal-Driven Clock Source

      56
    • Figure 3-5 Oscillator Configurations

      56
    • 3.4.3 External Source Clock

      56
    • 3.4.4 System Clocks

      57
    • Figure 3-6 Clock Organization

      57
    • 3.4.5 Power-Save Operation

      57
• Chap 4:Peripheral Control Block

  59
  • 4.1 Overview

    59
  • Figure 4-1 Peripheral Control Block Register Map

    60
  • 4.1.1 Peripheral Control Block Relocation Register

    62
  • Figure 4-2 PCB Relocation Register

    62
  • 4.1.2 Reset Configuration Register

    63
  • Figure 4-3 Reset Configuration Register

    63
  • 4.1.3 Processor Release Level Register

    64
  • Figure 4-4 Processor Release Level Register

    64
  • Table 4-1 PRL Values

    64
  • 4.1.4 Power-Save Control Register

    65
  • Figure 4-5 Power-Save Control Register

    65
  • 4.2 Initialization and Processor Reset

    66
  • Table 4-2 Initial Register State After Reset

    67
• Chap 5:Chip Select Unit

  69
  • 5.1 Overview

    69
  • Table 5-1 Chip Select Register Summary

    69
  • 5.2 Chip Select Timing

    70
  • 5.3 Ready and Wait-State Programming

    70
  • 5.4 Chip Select Overlap

    70
  • 5.5 Chip Select Registers

    71
  • 5.5.1 Upper Memory Chip Select Register (UMCS)

    72
  • Figure 5-1 Upper Memory Chip Select Register

    72
  • Table 5-2 UMCS Block Size Programming Values

    72
  • 5.5.2 Low Memory Chip Select Register (LMCS)

    74
  • Figure 5-2 Low Memory Chip Select Register

    74
  • Table 5-3 LMCS Block Size Programming Values

    74
  • 5.5.3 Midrange Memory Chip Select Register (MMCS)

    76
  • Figure 5-3 Midrange Memory Chip Select Register

    76
  • 5.5.4 PCS and MCS Auxiliary Register (MPCS)

    78
  • Figure 5-4 PCS and MCS Auxiliary Register

    78
  • Table 5-4 MCS Block Size Programming

    78
  • 5.5.5 Peripheral Chip Select Register (PACS)

    80
  • Figure 5-5 Peripheral Chip Select Register

    80
  • Table 5-5 PCS Address Ranges

    81
  • Table 5-6 PCS3–PCS0 Wait-State Encoding

    81
• Chap 6:Internal Memory

  83
  • 6.1 Overview

    83
  • 6.2 Interaction with External RAM

    83
  • 6.3 Emulator and Debug Modes

    84
  • 6.3.1 Internal Memory Disable

    84
  • 6.3.2 Show Read Enable

    84
  • 6.4 Internal Memory Chip Select Register (IMCS)

    85
  • Figure 6-1 Internal Memory Chip Select Register

    85
• Chap 7:Refresh Control Unit

  87
  • 7.1 Overview

    87
  • 7.1.1 Memory Partition Register (MDRAM)

    87
  • Figure 7-1 Memory Partition Register

    87
  • 7.1.2 Clock Prescaler Register (CDRAM)

    88
  • Figure 7-2 Clock Prescaler Register

    88
  • 7.1.3 Enable RCU Register (EDRAM)

    88
  • Figure 7-3 Enable RCU Register

    88
• Chap 8:Interrupt Control Unit

  89
  • 8.1 Overview

    89
    • 8.1.1 Definitions of Interrupt Terms

      89
    • Table 8-1 Interrupt Types

      91
    • 8.1.2 Interrupt Conditions and Sequence

      92
    • 8.1.3 Interrupt Priority

      93
    • 8.1.4 Software Exceptions, Traps, and NMI

      94
    • 8.1.5 Interrupt Acknowledge

      96
    • Figure 8-1 Interrupt Acknowledge Bus Cycle

      96
    • 8.1.6 Interrupt Controller Reset Conditions

      97
  • 8.2 Master Mode Operation

    98
    • 8.2.1 Fully Nested Mode

      98
    • Figure 8-2 Fully Nested Mode Interrupt Connections

      98
    • 8.2.2 Cascade Mode

      99
    • Figure 8-3 Cascade Mode Interrupt Connections

      99
    • 8.2.3 Special Fully Nested Mode

      100
    • 8.2.4 Operation in a Polled Environment

      100
    • 8.2.5 End-of-Interrupt Write to the EOI Register

      100
  • 8.3 Master Mode Interrupt Controller Registers

    101
    • Table 8-2 Interrupt Control Registers, Master Mode

      101
    • 8.3.1 INT0 and INT1 Control Registers (I0CON)

      102
    • Figure 8-4 INT0 and INT1 Control Registers

      102
    • Table 8-3 Priority Level

      103
    • 8.3.2 INT2 and INT3 Control Registers (I2CON)

      104
    • Figure 8-5 INT2 and INT3 Control Registers

      104
    • 8.3.3 INT4 Control Register (I4CON)

      105
    • Figure 8-6 INT4 Control Register

      105
    • 8.3.4 Timer and DMA Interrupt Control Registers

      106
    • Figure 8-7 Timer/DMA Interrupt Control Registers

      106
    • 8.3.5 Watchdog Timer Interrupt Control Register

      107
    • Figure 8-8 Watchdog Timer Interrupt Control

      107
    • 8.3.6 Serial Port Interrupt Control Register

      108
    • Figure 8-9 Serial Port Interrupt Control Register

      108
    • 8.3.7 Interrupt Status Register (INTSTS)

      109
    • Figure 8-10 Interrupt Status Register

      109
    • 8.3.8 Interrupt Request Register (REQST)

      110
    • Figure 8-11 Interrupt Request Register

      110
    • 8.3.9 In-Service Register (INSERV)

      111
    • Figure 8-12 In-Service Register

      111
    • 8.3.10 Priority Mask Register (PRIMSK)

      112
    • Figure 8-13 Priority Mask Register

      112
    • Table 8-4 Priority Field Mask (Master Mode)

      112
    • 8.3.11 Interrupt Mask Register (IMASK)

      113
    • Figure 8-14 Interrupt Mask Register

      113
    • 8.3.12 Poll Status Register (POLLST)

      114
    • Figure 8-15 Poll Status Register

      114
    • 8.3.13 Poll Register (POLL)

      115
    • Figure 8-16 Poll Register (POLL)

      115
    • 8.3.14 End-of-Interrupt Register (EOI)

      116
    • Figure 8-17 Example EOI Assembly Code

      116
    • Figure 8-18 End-of-Interrupt Register

      116
  • 8.4 Slave Mode Operation

    117
    • 8.4.1 Slave Mode Interrupt Nesting

      117
    • 8.4.2 Slave Mode Interrupt Controller Registers

      117
    • Table 8-5 Interrupt Controller Registers, Slave Mode

      117
    • 8.4.3 Timer and DMA Interrupt Control Registers

      118
    • Figure 8-19 Timer and DMA Interrupt Control Registers

      118
    • 8.4.4 Interrupt Status Register (INTSTS)

      119
    • Figure 8-20 Interrupt Status Register

      119
    • 8.4.5 Interrupt Request Register (REQST)

      120
    • Figure 8-21 Interrupt Request Register

      120
    • 8.4.6 In-Service Register (INSERV)

      121
    • Figure 8-22 In-Service Register

      121
    • 8.4.7 Priority Mask Register (PRIMSK)

      122
    • Figure 8-23 Priority Mask Register

      122
    • Table 8-6 Priority Field Mask (Slave Mode)

      122
    • 8.4.8 Interrupt Mask Register (IMASK)

      123
    • Figure 8-24 Interrupt Mask Register

      123
    • 8.4.9 Specific End-of-Interrupt Register (EOI)

      124
    • Figure 8-25 Specific End-of-Interrupt Register

      124
    • 8.4.10 Interrupt Vector Register (INTVEC)

      125
    • Figure 8-26 Interrupt Vector Register

      125
• Chap 9:Timer Control Unit

  127
  • 9.1 Overview

    127
  • 9.2 Programmable Registers

    127
  • Table 9-1 Timer Control Unit Register Summary

    127
  • 9.2.1 Timer Operating Frequency

    128
  • 9.2.2 Timer 0 and Timer 1 Mode and Control Registers

    129
  • Figure 9-1 Timer 0 and Timer 1 Mode and Control

    129
  • 9.2.3 Timer 2 Mode and Control Register

    131
  • Figure 9-2 Timer 2 Mode and Control Register

    131
  • 9.2.4 Timer Count Registers

    132
  • Figure 9-3 Timer Count Registers

    132
  • 9.2.5 Timer Maxcount Compare Registers

    133
  • Figure 9-4 Timer Maxcount Compare Registers

    133
• Chap 10:DMA Controller

  135
  • 10.1 Overview

    135
  • 10.2 DMA Operation

    135
  • Table 10-1 DMA Controller Register Summary

    135
  • Figure 10-1 DMA Unit Block Diagram

    136
  • 10.3 Programmable DMA Registers

    136
    • 10.3.1 DMA Control Registers (D0CON)

      137
    • Figure 10-2 DMA Control Registers

      137
    • Table 10-2 Synchronization Type

      138
    • 10.3.2 DMA Transfer Count Registers (D0TC)

      139
    • Figure 10-3 DMA Transfer Count Registers

      139
    • 10.3.3 DMA Destination Address High Register

      140
    • Figure 10-4 DMA Destination Address High Register ...

      140
    • 10.3.4 DMA Destination Address Low Register

      141
    • Figure 10-5 DMA Destination Address Low Register

      141
    • 10.3.5 DMA Source Address High Register

      142
    • Figure 10-6 DMA Source Address High Register

      142
    • 10.3.6 DMA Source Address Low Register

      143
    • Figure 10-7 DMA Source Address Low Register

      143
  • 10.4 DMA Requests

    144
    • Table 10-3 Maximum DMA Transfer Rates

      144
    • 10.4.1 Synchronization Timing

      145
    • Figure 10-8 Source-Synchronized DMA Transfers

      145
    • Figure 10-9 Destination Synchronized DMA Transfers

      146
    • 10.4.2 DMA Acknowledge

      146
    • 10.4.3 DMA Priority

      146
    • 10.4.4 DMA Programming

      146
    • 10.4.5 DMA Channels on Reset

      147
• Chap 11:Asynchronous Serial Port

  149
  • 11.1 Overview

    149
  • 11.2 Programmable Registers

    149
    • Table 11-1 Asynchronous Serial Port Register Summary

      149
    • 11.2.1 Serial Port Control Register (SPCT)

      150
    • Figure 11-1 Serial Port Control Register

      150
    • Table 11-2 Parity Mode Bit Settings

      151
    • 11.2.2 Serial Port Status Register (SPSTS)

      152
    • Figure 11-2 Serial Port Status Register

      152
    • 11.2.3 Serial Port Transmit Data Register (SPTD)

      153
    • Figure 11-3 Serial Port Transmit Data Register

      153
    • 11.2.4 Serial Port Receive Data Register (SPRD)

      154
    • Figure 11-4 Serial Port Receive Data Register

      154
    • 11.2.5 Serial Port Baud Rate Divisor Register (SPBAUD)

      155
    • Figure 11-5 Serial Port Baud Rate Divisor Register

      155
  • Table 11-3 Serial Port Baud Rate Table

    155
• Chap 12:Synchronous Serial Interface

  157
  • 12.1 Overview

    157
    • Table 12-1 Synchronous Serial Interface Summary

      157
    • 12.1.1 Four-Pin Interface

      158
  • 12.2 Programmable Registers

    158
    • 12.2.1 Synchronous Serial Status Register

      159
    • Figure 12-1 Synchronous Serial Status Register

      159
    • 12.2.2 Synchronous Serial Control Register

      160
    • Figure 12-2 Synchronous Serial Control Register

      160
    • Table 12-2 SCLK Divider Values

      160
    • 12.2.3 Synchronous Serial Transmit 1 Register

      161
    • Figure 12-3 Synchronous Serial Transmit Register

      161
    • 12.2.4 Synchronous Serial Receive Register

      162
    • Figure 12-4 Synchronous Serial Receive Register

      162
  • 12.3 SSI Programming

    163
    • Figure 12-5 SSI Multiple Write

      164
    • Figure 12-6 SSI Multiple Read

      164
• Chap 13:Programmable I/O Pins

  165
  • 13.1 Overview

    165
    • Figure 13-1 Programmable I/O Pin Operation

      165
    • Table 13-1 PIO Pin Assignments and Register Bits

      166
  • 13.2 PIO Mode Registers

    167
    • Table 13-2 PIO Mode and PIO Direction Settings

      167
    • Figure 13-2 PIO Mode 1 Register (PIOMODE1)

      167
    • Figure 13-3 PIO Mode 0 Register (PIOMODE0)

      167
    • 13.2.1 PIO Mode 1 Register

      167
    • 13.2.2 PIO Mode 0 Register

      167
  • 13.3 PIO Direction Registers

    168
    • Figure 13-4 PIO Direction 1 Register (PDIR1)

      168
    • Figure 13-5 PIO Direction 0 Register (PDIR0)

      168
    • 13.3.1 PIO Direction 1 Register

      168
    • 13.3.2 PIO Direction 0 Register

      168
  • 13.4 PIO Data Registers

    169
    • Figure 13-6 PIO Data 1 Register (PDATA1)

      169
    • Figure 13-7 PIO Data 0 Register (PDATA0)

      169
    • 13.4.1 PIO Data Register 1

      169
    • 13.4.2 PIO Data Register 0

      169
  • 13.5 Open-Drain Outputs

    169
• Appendix A:Register Summary

  171
  • Table A-1 Internal Register Summary

    172
  • Figure A-1 Internal Register Summary

    174
• Index

  187