BenutzerhandbuchInhaltsverzeichnisContents5About the NS752015NS7520 Features16Key features and operating modes of the major NS7520 modules16NS7520 module block diagram19Operating frequency20Pinout and Packaging21Packaging22Pinout detail tables and signal descriptions25System bus interface26Chip select controller30Ethernet interface MAC32“No connect” pins35General-purpose I/O35System clock and reset38System mode (test support)39JTAG test (ARM debugger)40Power supply42Working with the CPU43ARM Thumb concept44CPU performance44Working with ARM exceptions45Summary of ARM exceptions46Exception priorities46Exception vector table47Detail of ARM exceptions48Entering and exiting an exception (software action)51Hardware Interrupts53FIRQ and IRQ lines53Interrupt controller53Interrupt sources54BBus Module57BBus masters and slaves58Cycles and BBus arbitration58Address decoding59SYS Module61Signal description62JTAG support62ARM debug63System clock generation (NS7520 clock module)63External oscillator vs. internal PLL circuit63NS7520 clock module block diagram64Using the external oscillator64External oscillator mode hardware configuration65Using the PLL circuit66PLL mode hardware configuration66Setting the PLL frequency68PLL Settings register: Setting the PLL frequency on bootup68PLL Control register: Setting the PLL frequency with the PLL Control register71Reset circuit sources73NS7520 bootstrap initialization74GEN Module75Module configuration76GEN module hardware initialization76GEN module registers77System Control register77System Status register82Software Service register84Timer Control registers84Timer Status registers87PORTA Configuration register88PORTC Configuration register91Interrupts94Interrupt controller registers95Memory Controller Module99About the MEM module100MEM module hardware initialization100Pin configuration100MEM module configuration102Setting the chip select address range102Memory Module Configuration register104Chip Select Base Address register107Chip Select Option Register A111Chip Select Option Register B115Static memory (SRAM) controller116Single cycle read/write117Burst cycles118NS7520 DRAM address multiplexing119Using the internal multiplexer119Using the external multiplexer122DRAM refresh123FP/EDO DRAM controller123Single cycle read/write124FP/EDO DRAM burst cycles125SDRAM125NS7520 SDRAM interconnect126SDRAM A10/AP support130Command definitions131Memory timing fields - SDRAM132BSIZE configuration132SDRAM Mode register133SDRAM read cycles134SDRAM write cycles136Peripheral page burst size138DMA Module141DMA module142Fly-by operation transfers142Memory-to-memory operation143DMA buffer descriptor144DMA channel assignments147DMA channel registers148Address map148Buffer Descriptor Pointer register150DMA Control register150DMA Status/Interrupt Enable register156Ethernet transmitter considerations158Ethernet receiver considerations159External peripheral DMA support159Signal description160External DMA configuration160Memory-to-memory mode160DMA controller reset161Ethernet Module163Ethernet front-end (EFE)164Transmit and receive FIFOs165EFE transmit processing165EFE receive processing165Receive buffer descriptor selection166External CAM filtering167MAC module168MAC module block diagram168DMA channel assignments170EFE configuration170Ethernet General Control register (EGCR) bit definitions172Ethernet General Status register (EGSR) bit definitions178Ethernet FIFO Data register181Ethernet Transmit Status register183Ethernet Receive Status register188MAC Configuration Register 1192MAC Configuration Register 2194Back-to-Back Inter-Packet-Gap register198Non-Back-to-Back Inter-Packet-Gap register199Collision Window/Collision Retry register200Maximum Frame register201PHY Support register202Test register203MII Management Configuration register205MII Management Command register207MII Management Address register208MII Management Write Data register209MII Management Read Data register210MII Management Indicators register211SMII Status register212Station Address registers212Station Address Filter register215Register hash table216Serial Controller Module223Supported features224Bit-rate generator225Serial protocols226UART mode226SPI mode227FIFO management228General-purpose I/O configurations236Serial port performance237Configuration237Serial Channel registers239Serial Channel 1, 2 Control Register A239Serial Channel 1, 2 Control Register B245Serial Channel 1, 2 Status Register A249Serial Channel 1, 2 Bit-Rate registers258Serial Channel 1, 2 FIFO registers268Serial Channel 1, 2 Receive Buffer Gap Timer269Serial Channel 1, 2 Receive Character Gap Timer270Serial Channel 1,2 Receive Match register272Serial Channel 1, 2 Receive Match MASK register272Electrical Characteristics275DC characteristics276Recommended operating conditions276Input/Output characteristics277Pad pullup and pulldown characteristics277Absolute maximum ratings279AC characteristics279AC electrical specifications279Oscillator Characteristics281Timing Diagrams283Timing_Specifications283Reset_timing284SRAM timing285SDRAM timing295FP DRAM timing303Ethernet timing310JTAG timing312External DMA timing314Serial internal/external timing317GPIO timing319Index321Größe: 1,67 MBSeiten: 332Language: EnglishHandbuch öffnen
