Benutzerhandbuch für Digi NS9750

Inhaltsverzeichnis

• C h a p t e r 1 : A b o u t N S 9 7 5 0

  1
• NS9750 Features

  2
• System-level interfaces

  8
• System boot

  10
• Reset

  10
• RESET_DONE as an input

  11
• RESET_DONE as an output

  11
• System clock

  13
• USB clock

  15
• C h a p t e r 2 : N S 9 7 5 0 P i n o u t

  17
• Pinout and signal descriptions

  18
• System Memory interface

  18
• System Memory interface signals

  22
• Ethernet interface

  25
• Clock generation/system pins

  26
• bist_en_n, pll_test_n, and scan_en_n

  28
• PCI interface

  28
• GPIO MUX

  34
• LCD module signals

  42
• I2C interface

  43
• USB interface

  43
• JTAG interface for ARM core/boundary scan

  43
• Reserved

  45
• Power ground

  46
• C h a p t e r 3 : W o r k i n g w i t h t h e C P U

  47
• About the processor

  48
• Instruction sets

  49
• ARM instruction set

  50
• Thumb instruction set

  50
• Java instruction set

  50
• System control processor (CP15) registers

  51
• ARM926EJ-S system addresses

  51
• Accessing CP15 registers

  52
• Terms and abbreviations

  52
• Register summary

  53
• R0: ID code and cache type status registers

  55
• R1: Control register

  58
• R2: Translation Table Base register

  61
• R3: Domain Access Control register

  61
• R4 register

  62
• R5: Fault Status registers

  62
• R6: Fault Address register

  64
• R7: Cache Operations register

  64
• R8:TLB Operations register

  68
• R9: Cache Lockdown register

  69
• R10: TLB Lockdown register

  73
• R11 and R12 registers

  74
• R13: Process ID register

  75
• R14 register

  77
• R15: Test and debug register

  77
• Jazelle (Java)

  77
• DSP

  78
• Memory Management Unit (MMU)

  78
• MMU Features

  78
• Address translation

  81
• MMU faults and CPU aborts

  95
• Domain access control

  98
• Fault checking sequence

  99
• External aborts

  102
• Enabling the MMU

  103
• Disabling the MMU

  104
• TLB structure

  104
• Caches and write buffer

  105
• Cache features

  105
• Write buffer

  106
• Enabling the caches

  107
• Cache MVA and Set/Way formats

  109
• Noncachable instruction fetches

  111
• Self-modifying code

  112
• AHB behavior

  112
• Instruction Memory Barrier

  113
• IMB operation

  113
• Sample IMB sequences

  114
• C h a p t e r 4 : S y s t e m C o n t r o l M o d u l e

  115
• System Control Module features

  116
• Bus interconnection

  116
• System bus arbiter

  116
• Arbiter configuration examples

  120
• Address decoding

  123
• Programmable timers

  125
• Software watchdog timer

  125
• General purpose timers/counters

  125
• Interrupt controller

  129
• Vectored interrupt controller (VIC) flow

  132
• System attributes

  133
• PLL configuration

  133
• Bootstrap initialization

  134
• System configuration registers

  138
• AHB Arbiter Gen Configuration register

  144
• BRC0, BRC1, BRC2, and BRC3 registers

  145
• Timer 0–15 Reload Count registers

  146
• Timer 0–15 Read register

  147
• Interrupt Vector Address Register Level 0–31

  147
• Int (Interrupt) Config (Configuration) registers (0–31)

  148
• ISRADDR register

  150
• Interrupt Status Active

  151
• Interrupt Status Raw

  152
• Timer Interrupt Status register

  153
• Software Watchdog Configuration register

  153
• Software Watchdog Timer register

  155
• Clock Configuration register

  155
• Reset and Sleep Control register

  157
• Miscellaneous System Configuration and Status register

  158
• PLL Configuration register

  161
• Active Interrupt Level Status register

  163
• Timer 0–15 Control registers

  163
• Gen ID register

  173
• External Interrupt 0–3 Control register

  175
• C h a p t e r 5 : M e m o r y C o n t r o l l e r

  177
• Features

  178
• System overview

  179
• Low-power operation

  180
• Memory map

  180
• Static memory controller

  183
• Write protection

  184
• Extended wait transfers

  184
• Memory mapped peripherals

  185
• Static memory initialization

  185
• Byte lane control

  211
• Address connectivity

  212
• Byte lane control and databus steering

  216
• Dynamic memory controller

  224
• Write protection

  224
• Access sequencing and memory width

  224
• Address mapping

  225
• Registers

  264
• Register map

  264
• Reset values

  266
• Control register

  267
• Status register

  269
• Configuration register

  269
• Dynamic Memory Control register

  270
• Dynamic Memory Refresh Timer register

  272
• Dynamic Memory Read Configuration register

  274
• Dynamic Memory Precharge Command Period register

  275
• Dynamic Memory Active to Precharge Command Period register

  276
• Dynamic Memory Self-refresh Exit Time register

  277
• Dynamic Memory Last Data Out to Active Time register

  278
• Dynamic Memory Data-in to Active Command Time register

  279
• Dynamic Memory Write Recovery Time register

  280
• Dynamic Memory Active to Active Command Period register

  281
• Dynamic Memory Auto Refresh Period register

  282
• Dynamic Memory Exit Self-refresh register

  283
• Dynamic Memory Active Bank A to Active Bank B Time register

  284
• Static Memory Extended Wait register

  286
• Dynamic Memory Configuration 0–3 registers

  287
• Dynamic Memory RAS and CAS Delay 0–3 registers

  291
• Static Memory Configuration 0–3 registers

  292
• Static Memory Write Enable Delay 0–3 registers

  296
• Static Memory Output Enable Delay 0–3 registers

  297
• Static Memory Read Delay 0–3 registers

  298
• Static Memory Page Mode Read Delay 0–3 registers

  299
• Static Memory Write Delay 0–3 registers

  300
• Static Memory Turn Round Delay 0–3 registers

  301
• C h a p t e r 6 : E t h e r n e t C o m m u n i c a t i o n M o d u l e

  315
• Overview

  316
• Ethernet MAC

  317
• Station address logic (SAL)

  321
• Statistics module

  321
• Ethernet front-end module

  323
• Receive packet processor

  324
• Transmit packet processor

  327
• Ethernet Slave Interface

  330
• Interrupts

  331
• Resets

  332
• External CAM filtering

  334
• Ethernet Control and Status registers

  337
• Ethernet General Control Register #1

  339
• Ethernet General Control Register #2

  342
• Ethernet General Status register

  344
• Ethernet Transmit Status register

  344
• Ethernet Receive Status register

  347
• MAC Configuration Register #1

  348
• MAC Configuration Register #2

  351
• Back-to-Back Inter-Packet-Gap register

  354
• Non Back-to-Back Inter-Packet-Gap register

  355
• Collision Window/Retry register

  355
• Maximum Frame register

  357
• PHY Support register

  358
• MII Management Configuration register

  359
• MII Management Command register

  360
• MII Management Address register

  361
• MII Management Write Data register

  362
• MII Management Read Data register

  363
• MII Management Indicators register

  363
• Station Address registers

  364
• Station Address Filter register

  366
• Register Hash Tables

  366
• Statistics registers

  368
• RX_A Buffer Descriptor Pointer register

  383
• RX_B Buffer Descriptor Pointer register

  383
• RX_C Buffer Descriptor Pointer register

  384
• RX_D Buffer Descriptor Pointer register

  384
• Ethernet Interrupt Status register

  385
• Ethernet Interrupt Enable register

  387
• TX Buffer Descriptor Pointer register

  389
• Transmit Recover Buffer Descriptor Pointer register

  389
• TX Error Buffer Descriptor Pointer register

  390
• RX_A Buffer Descriptor Pointer Offset register

  391
• RX_B Buffer Descriptor Pointer Offset register

  392
• RX_C Buffer Descriptor Pointer Offset register

  393
• RX_D Buffer Descriptor Pointer Offset register

  393
• Transmit Buffer Descriptor Pointer Offset register

  394
• RX Free Buffer register

  395
• TX buffer descriptor RAM

  396
• Sample hash table code

  397
• C h a p t e r 7 : P C I - t o - A H B B r i d g e

  403
• About the PCI-to-AHB Bridge

  404
• PCI-to-AHB bridge functionality

  405
• Cross-bridge transaction error handling

  407
• AHB address decoding and translation

  408
• PCI address decoding and mapping

  408
• Interrupts

  409
• Transaction ordering

  410
• Endian configuration

  411
• Configuration registers

  411
• Bridge Configuration registers

  413
• PCI bus arbiter

  418
• PCI arbiter functional description

  419
• Slave interface

  420
• PCI Arbiter Configuration registers

  420
• PCI system configurations

  456
• Device selection for configuration

  458
• PCI interrupts

  458
• PCI central resource functions

  458
• CardBus Support

  461
• Configuring NS9750 for CardBus support

  463
• CardBus adapter requirements

  464
• CardBus interrupts

  465
• C h a p t e r 8 : B B u s B r i d g e

  467
• BBus bridge functions

  468
• Bridge control logic

  469
• DMA accesses

  471
• BBus control logic

  472
• BBus bridge masters and slaves

  472
• Cycles and BBus arbitration

  473
• BBus peripheral address map (decoding)

  473
• Two-channel AHB DMA controller (AHB bus)

  474
• DMA buffer descriptor

  474
• Descriptor list processing

  476
• Peripheral DMA read access

  477
• Peripheral DMA write access

  478
• Peripheral REQ signaling

  479
• Design Limitations

  480
• Calculating AHB DMA response latency

  480
• Static RAM chip select configuration

  482
• Interrupt aggregation

  483
• Bandwidth requirements

  483
• SPI-EEPROM boot logic

  484
• Serial Channel B configuration

  485
• Memory Controller configuration

  486
• SDRAM boot algorithm

  488
• BBus Bridge Control and Status registers

  490
• Buffer Descriptor Pointer register

  491
• DMA Channel 1/2 Control register

  491
• DMA Status and Interrupt Enable register

  494
• DMA Peripheral Chip Select register

  496
• BBus Bridge Interrupt Status register

  498
• BBus Bridge Interrupt Enable register

  499
• C h a p t e r 9 : B B u s D M A C o n t r o l l e r

  501
• About the BBus DMA controllers

  502
• DMA context memory

  503
• DMA buffer descriptor

  504
• DMA channel assignments

  509
• DMA Control and Status registers

  510
• DMA Buffer Descriptor Pointer

  512
• DMA Control register

  514
• DMA Status/Interrupt Enable register

  516
• C h a p t e r 1 0 : B B u s U t i l i t y

  521
• BBus Utility Control and Status registers

  522
• Master Reset register

  523
• GPIO Configuration registers

  524
• GPIO Control registers

  529
• GPIO Status registers

  532
• BBus Monitor register

  535
• BBus DMA Interrupt Status register

  536
• BBus DMA Interrupt Enable register

  537
• USB Configuration register

  538
• Endian Configuration register

  539
• ARM Wake-up register

  541
• C h a p t e r 1 1 : I 2 C M a s t e r / S l a v e I n t e r f a c e

  543
• Overview

  544
• Physical I2C bus

  544
• I2C external addresses

  545
• I2C command interface

  545
• Locked interrupt driven mode

  546
• Master module and slave module commands

  546
• Bus arbitration

  547
• I2C registers

  547
• Command Transmit Data register

  548
• Status Receive Data register

  549
• Master Address register

  550
• Slave Address register

  551
• Configuration register

  552
• Interrupt Codes

  553
• Software driver

  555
• Flow charts

  556
• Master module (normal mode, 16-bit)

  556
• Slave module (normal mode, 16-bit)

  557
• C h a p t e r 1 2 : L C D C o n t r o l l e r

  559
• LCD features

  560
• Programmable parameters

  560
• LCD panel resolution

  561
• LCD panel support

  561
• Number of colors

  562
• LCD power up and power down sequence support

  563
• LCD controller functional overview

  564
• Clocks

  565
• Signals and interrupts

  566
• AHB interface

  568
• AHB master and slave interfaces

  568
• Dual DMA FIFOs and associated control logic

  568
• Pixel serializer

  569
• RAM palette

  573
• Grayscaler

  574
• Upper and lower panel formatters

  574
• Panel clock generator

  574
• Timing controller

  574
• Generating interrupts

  575
• External pad interface signals

  575
• LCD panel signal multiplexing details

  575
• Registers

  579
• LCDTiming0

  580
• LCDTiming1

  582
• LCDTiming2 register

  583
• LCDTiming3

  587
• LCDUPBASE and LCDLPBASE

  587
• LCDINTRENABLE

  589
• LCDControl register

  590
• LCDStatus register

  593
• LCDInterrupt register

  594
• LCDUPCURR and LCDLPCURR

  594
• LCDPalette register

  595
• Interrupts

  598
• MBERRORINTR — Master bus error interrupt

  598
• VCOMPINTR — Vertical compare interrupt

  598
• LBUINTR — Next base address update interrupt

  599
• C h a p t e r 1 3 : S e r i a l C o n t r o l M o d u l e : U A R T

  601
• Features

  602
• Bit-rate generator

  603
• UART mode

  604
• FIFO management

  605
• Transmit FIFO interface

  605
• Receive FIFO interface

  606
• Serial port performance

  608
• Serial port control and status registers

  608
• Serial Channel B/A/C/D Control Register A

  611
• Serial Channel B/A/C/D Control Register B

  614
• Serial Channel B/A/C/D Status Register A

  617
• Serial Channel B/A/C/D Bit-rate register

  624
• Serial Channel B/A/C/D FIFO Data register

  629
• Serial Channel B/A/C/D Receive Buffer GAP Timer

  630
• Serial Channel B/A/C/D Receive Character GAP Timer

  632
• Serial Channel B/A/C/D Receive Match register

  634
• Serial Channel B/A/C/D Receive Match MASK register

  635
• Serial Channel B/A/C/D Flow Control register

  636
• Serial Channel B/A/C/D Flow Control Force register

  638
• C h a p t e r 1 4 : S e r i a l C o n t r o l M o d u l e : S P I

  643
• Features

  644
• Bit-rate generator

  645
• SPI mode

  646
• SPI modes

  646
• FIFO management

  647
• Transmit FIFO interface

  647
• Receive FIFO interface

  648
• Serial port performance

  650
• Serial port control and status registers

  650
• Serial Channel B/A/C/D Control Register A

  652
• Serial Channel B/A/C/D Control Register B

  655
• Serial Channel B/A/C/D Status Register A

  657
• Serial Channel B/A/C/D Bit-rate register

  660
• Serial Channel B/A/C/D FIFO Data register

  665
• C h a p t e r 1 5 : I E E E 1 2 8 4 P e r i p h e r a l C o n t r o l l e r

  669
• Requirements

  670
• Overview

  670
• Compatibility mode

  671
• Nibble mode

  672
• Byte mode

  672
• ECP mode

  673
• Data and command FIFOs

  675
• IEEE 1284 negotiation

  676
• BBus slave and DMA interface

  677
• BBus slave and DMA interface register map

  677
• IEEE 1284 General Configuration register

  679
• Interrupt Status and Control register

  681
• FIFO Status register

  684
• Forward Command FIFO Read register

  686
• Forward Data FIFO Read register

  687
• Reverse FIFO Write register/Reverse FIFO Write Register — Last

  687
• Forward Command DMA Control register

  689
• Forward Data DMA Control register

  690
• Printer Data Pins register

  691
• Port Status register, host

  692
• Port Control register

  693
• Port Status register, peripheral

  694
• Feature Control Register A

  694
• Feature Control Register B

  695
• Interrupt Enable register

  695
• Master Enable register

  697
• Extensibility Byte Requested by Host

  698
• Extended Control register

  698
• Interrupt Status register

  699
• Pin Interrupt Mask register

  700
• Pin Interrupt Control register

  701
• Granularity Count register

  702
• Forward Address register

  703
• Core Phase (IEEE1284) register

  704
• C h a p t e r 1 6 : U S B C o n t r o l l e r M o d u l e

  707
• Overview

  708
• USB module architecture

  708
• USB device block

  710
• Control and status

  710
• Packet and data flow

  711
• Logical and physical endpoints

  712
• Slew rates

  712
• Host block

  712
• Control and status

  712
• Packet data flow

  713
• USB device endpoint

  714
• Transmission error handling

  714
• Handling USB-IN packet errors

  715
• Handling USB-OUT packet errors

  715
• USB block registers

  716
• USB Global registers

  716
• Global Control and Status register

  717
• Device Control and Status register

  718
• Global Interrupt Enable register

  720
• Global Interrupt Status register

  721
• Device IP Programming Control/Status register

  724
• USB host block registers

  725
• Reserved bits

  725
• USB host block register address map

  725
• HCRevision register

  726
• HcControl register

  727
• HcCommandStatus register

  730
• HcInterruptStatus register

  733
• HcInterruptEnable register

  735
• HcInterruptDisable register

  737
• HcHCCA register

  739
• HcPeriodCurrentED register

  740
• HcControlHeadED register

  741
• HcControlCurrentED register

  742
• HcBulkHeadED register

  743
• HcBulkCurrentED register

  744
• HcDoneHead register

  746
• HcFmInterval register

  747
• HcFmRemaining register

  748
• HcFmNumber register

  749
• HcPeriodicStart register

  750
• HcLsThreshold register

  751
• Root hub partition registers

  752
• HcRhDescriptorA register

  753
• HcRhDescriptorB register

  755
• HcRhStatus register

  756
• HcRhPortStatus[1] register

  759
• USB Device Block registers

  765
• Device Descriptor/Setup Command register

  765
• Endpoint Descriptor #0–#11 registers

  766
• USB Device Endpoint FIFO Control and Data registers

  767
• FIFO Interrupt Status registers

  769
• FIFO Interrupt Enable registers

  776
• FIFO Packet Control registers

  780
• FIFO Status and Control registers

  781
• C h a p t e r 1 7 : T i m i n g

  787
• Electrical characteristics

  788
• Absolute maximum ratings

  788
• Recommended operating conditions

  788
• Maximum power dissipation

  789
• Typical power dissipation

  789
• DC electrical characteristics

  790
• Inputs

  790
• Outputs

  791
• Reset and edge sensitive input timing requirements

  792
• Power sequencing

  794
• Memory timing

  795
• SDRAM burst read (16-bit)

  796
• SDRAM burst read (16-bit), CAS latency = 3

  797
• SDRAM burst write (16-bit)

  798
• SDRAM burst read (32-bit)

  799
• SDRAM burst read (32-bit), CAS latency = 3

  800
• SDRAM burst write (32-bit)

  801
• SDRAM load mode

  802
• SDRAM refresh mode

  803
• Clock enable timing

  803
• Static RAM read cycles with 0 wait states

  805
• Static RAM asynchronous page mode read, WTPG = 1

  806
• Static RAM read cycle with configurable wait states

  807
• Static RAM sequential write cycles

  808
• Static RAM write cycle

  809
• Static write cycle with configurable wait states

  810
• Slow peripheral acknowledge timing

  811
• Ethernet timing

  813
• Ethernet MII timing

  814
• Ethernet RMII timing

  815
• PCI timing

  816
• Internal PCI arbiter timing

  818
• PCI burst write from NS9750 timing

  818
• PCI burst read from NS9750 timing

  819
• PCI burst write to NS9750 timing

  819
• PCI burst read to NS9750 timing

  820
• PCI clock timing

  820
• I2C timing

  821
• LCD timing

  822
• Horizontal timing for STN displays

  824
• Vertical timing for STN displays

  825
• Horizontal timing for TFT displays

  825
• Vertical timing for TFT displays

  825
• HSYNC vs VSYNC timing for STN displays

  826
• HSYNC vs VSYNC timing for TFT displays

  826
• LCD output timing

  826
• SPI timing

  827
• master mode 0 and 1: 2-byte transfer

  829
• master mode 2 and 3: 2-byte transfer

  829
• slave mode 0 and 1: 2-byte transfer

  830
• slave mode 2 and 3: 2-byte transfer

  830
• IEEE 1284 timing

  831
• IEEE 1284 timing example

  831
• USB timing

  832
• USB differential data timing

  833
• USB full speed load timing

  833
• USB low speed load

  834
• Reset and hardware strapping timing

  835
• JTAG timing

  836
• Clock timing

  837
• USB crystal/external oscillator timing

  837
• LCD input clock timing

  838
• System PLL bypass mode timing

  839
• C h a p t e r 1 8 : P a c k a g i n g

  841
• Product specifications

  845