Benutzerhandbuch für Emerson MVME2500

Inhaltsverzeichnis

• MVME2500

  1
• Contents

  3
• About this Manual

  13
  • Overview of Contents

    13
  • Abbreviations

    13
  • Conventions

    15
  • Summary of Changes

    17
• Introduction

  19
  • 1.1 Overview

    19
  • 1.2 Standard Compliances

    21
  • 1.3 Mechanical Data

    22
  • 1.4 Ordering Information

    22
  • 1.5 Product Identification

    24
• Hardware Preparation and Installation

  25
  • 2.1 Overview

    25
  • 2.2 Unpacking and Inspecting the Board

    26
  • 2.3 Requirements

    26
    • 2.3.1 Environmental Requirements

      27
    • 2.3.2 Power Requirements

      28
    • 2.3.3 Equipment Requirements

      29
  • 2.4 Configuring the Board

    29
  • 2.5 Installing Accessories

    30
    • 2.5.1 Rear Transition Module

      30
    • 2.5.2 PMC/XMC Support

      31
  • 2.6 Installing and Removing the Board

    32
  • 2.7 Completing the Installation

    34
• Controls, LEDs, and Connectors

  35
  • 3.1 Board Layout

    35
  • 3.2 Front Panel

    36
    • 3.2.1 Reset Switch

      37
  • 3.3 LEDs

    37
    • 3.3.1 Front Panel LEDs

      37
    • 3.3.2 Onboard LEDs

      39
  • 3.4 Connectors

    39
    • 3.4.1 Front Panel Connectors

      40
      • 3.4.1.1 RJ45 with Integrated Magnetics (J1)

        40
      • 3.4.1.2 Front Panel Serial Port (J4)

        41
      • 3.4.1.3 USB Connector (J5)

        42
      • 3.4.1.4 VMEBus P1 Connector

        42
      • 3.4.1.5 VMEBus P2 Connector

        44
    • 3.4.2 Onboard Connectors

      45
      • 3.4.2.1 Flash Program Connector (P7)

        45
      • 3.4.2.2 SATA Connector (J3)

        46
      • 3.4.2.3 PMC Connectors

        47
      • 3.4.2.4 JTAG Connector (P6)

        52
      • 3.4.2.5 COP Connector (P6)

        54
      • 3.4.2.6 SD Connector (J2)

        54
      • 3.4.2.7 XMC Connector (XJ2)

        55
      • 3.4.2.8 Miscellaneous P2020 Debug Connectors

        56
  • 3.5 Switches

    57
    • 3.5.1 Geographical Address Switch (S1)

      57
    • 3.5.2 SMT Configuration Switch (S2)

      59
• Functional Description

  61
  • 4.1 Block Diagram

    61
  • 4.2 Chipset

    61
    • 4.2.1 e500 Processor Core

      62
    • 4.2.2 Integrated Memory Controller

      62
    • 4.2.3 PCI Express Interface

      63
    • 4.2.4 Local Bus Controller (LBC)

      63
    • 4.2.5 Secure Digital Hub Controller (SDHC)

      63
    • 4.2.6 I2C Interface

      63
    • 4.2.7 USB Interface

      63
    • 4.2.8 DUART

      64
    • 4.2.9 DMA Controller

      64
    • 4.2.10 Enhanced Three-Speed Ethernet Controller (eTSEC)

      64
    • 4.2.11 General Purpose I/O (GPIO)

      64
    • 4.2.12 Security Engine (SEC) 3.1

      64
    • 4.2.13 Common On-Chip Processor (COP)

      65
    • 4.2.14 P20x0 Hardware Configuration Pins

      65
  • 4.3 System Memory

    65
  • 4.4 Timers

    65
    • 4.4.1 Real Time Clock

      65
    • 4.4.2 Internal Timer

      66
    • 4.4.3 Watchdog Timer

      66
    • 4.4.4 FPGA Tick Timer

      66
  • 4.5 Ethernet Interfaces

    66
  • 4.6 SPI Bus Interface

    67
    • 4.6.1 SPI Flash Memory

      67
    • 4.6.2 SPI Flash Programming

      67
    • 4.6.3 Firmware Redundancy

      68
    • 4.6.4 Crisis Recovery

      70
  • 4.7 Front UART Control

    70
  • 4.8 Rear UART Control

    71
  • 4.9 PMC/XMC Sites

    71
    • 4.9.1 PMC Add-on Card

      72
    • 4.9.2 XMC Add-on Card

      72
  • 4.10 SATA Interface

    72
  • 4.11 VME Support

    73
    • 4.11.1 Tsi148 VME Controller

      73
  • 4.12 USB

    73
  • 4.13 I2C Devices

    73
  • 4.14 Reset/Control FPGA

    74
  • 4.15 Power Management

    74
    • 4.15.1 Onboard Voltage Supply Requirement

      74
    • 4.15.2 Power Up Sequencing Requirements

      75
  • 4.16 Clock Structure

    76
  • 4.17 Reset Structure

    76
    • 4.17.1 Reset Sequence

      77
  • 4.18 Thermal Management

    77
  • 4.19 Real-Time Clock Battery

    77
  • 4.20 Debugging Support

    78
    • 4.20.1 POST Code Indicator

      78
    • 4.20.2 JTAG Chain and Board

      78
    • 4.20.3 Custom Debugging

      79
  • 4.21 Rear Transition Module (RTM)

    79
• Memory Maps and Registers

  81
  • 5.1 Overview

    81
  • 5.2 Memory Map

    81
  • 5.3 Flash Memory Map

    82
  • 5.4 Linux Devices Memory Map

    82
  • 5.5 Programmable Logic Device (PLD) Registers

    84
    • 5.5.1 PLD Revision Register

      84
    • 5.5.2 PLD Year Register

      84
    • 5.5.3 PLD Month Register

      85
    • 5.5.4 PLD Day Register

      85
    • 5.5.5 PLD Sequence Register

      85
    • 5.5.6 PLD Power Good Monitor Register

      86
    • 5.5.7 PLD LED Control Register

      87
    • 5.5.8 PLD PCI/PMC/XMC Monitor Register

      88
    • 5.5.9 PLD U-Boot and TSI Monitor Register

      89
    • 5.5.10 PLD Boot Bank Register

      89
    • 5.5.11 PLD Write Protect and I2C Debug Register

      91
    • 5.5.12 PLD Test Register 1

      93
    • 5.5.13 PLD Test Register 2

      93
    • 5.5.14 PLD GPIO2 Interrupt Register

      94
    • 5.5.15 PLD Shutdown and Reset Control and Reset Reason Register

      95
    • 5.5.16 PLD Watchdog Timer Refresh Register

      96
    • 5.5.17 PLD Watchdog Control Register

      97
    • 5.5.18 PLD Watchdog Timer Count Register

      97
  • 5.6 External Timer Registers

    98
    • 5.6.1 Prescaler Register

      98
    • 5.6.2 Control Registers

      99
    • 5.6.3 Compare High and Low Word Registers

      100
    • 5.6.4 Counter High and Low Word Registers

      101
• Boot System

  103
  • 6.1 Overview

    103
  • 6.2 Accessing U-Boot

    103
  • 6.3 Boot Options

    104
    • 6.3.1 Booting from a Network

      104
    • 6.3.2 Booting from an Optional SATA Drive

      105
    • 6.3.3 Booting from a USB Drive

      105
    • 6.3.4 Booting from an SD Card

      106
    • 6.3.5 Booting VxWorks Through the Network

      106
  • 6.4 Using the Persistent Memory Feature

    107
  • 6.5 MVME2500 Specific U-Boot Commands

    108
  • 6.6 Updating U-Boot

    110
• Programming Model

  113
  • 7.1 Overview

    113
  • 7.2 Reset Configuration

    113
  • 7.3 Interrupt Controller

    117
  • 7.4 I2C Bus Device Addressing

    118
  • 7.5 Ethernet PHY Address

    118
  • 7.6 Other Software Considerations

    119
    • 7.6.1 MRAM

      119
    • 7.6.2 Real Time Clock

      119
    • 7.6.3 Quad UART

      119
    • 7.6.4 LBC Timing Parameters

      120
  • 7.7 Clock Distribution

    121
    • 7.7.1 System Clock

      122
    • 7.7.2 Real Time Clock Input

      123
    • 7.7.3 Local Bus Controller Clock Divisor

      123
• A Replacing the Battery

  125
  • A.1 Replacing the Battery

    125
• B Related Documentation

  129
  • B.1 Emerson Network Power - Embedded Computing Documents

    129
  • B.2 Manufacturers’ Documents

    130
  • B.3 Related Specifications

    130
• Safety Notes

  133
• Sicherheitshinweise

  137
• Index

  143