Benutzerhandbuch für Epson S1D13708

Inhaltsverzeichnis

• S1D13708 TECHNICAL MANUAL

  1
  • COMPREHENSIVE SUPPORT TOOLS

    3
    • Documentation

      3
    • Evaluation/Demonstration Board

      3
  • Application Engineering Support

    3
    • Application Engineering Support

      3
• S1D13708 Embedded Memory LCD Controller July 2001

  5
  • FEATURES

    5
  • System Block Diagram

    5
  • DESCRIPTION

    6
    • Memory Interface

      6
    • CPU Interface

      6
    • Display Support

      6
    • Power Down Modes

      6
    • Display Modes

      6
    • Clock Source

      6
    • Operating Voltage

      6
    • Package

      6
• Hardware Functional Specification

  7
  • Table of Contents

    9
  • List of Tables

    13
  • List of Figures

    17
  • 1 Introduction

    21
    • 1.1 Scope

      21
    • 1.2 Overview Description

      21
  • 2 Features

    22
    • 2.1 Integrated Frame Buffer

      22
    • 2.2 CPU Interface

      22
    • 2.3 Display Support

      22
    • 2.4 Display Modes

      23
    • 2.5 Display Features

      23
    • 2.6 Clock Source

      23
    • 2.7 Operating Voltage

      24
    • 2.8 Miscellaneous

      24
  • 3 Typical System Implementation Diagrams

    25
    • Figure 31 Typical System Diagram (Generic #1 Bus)

      25
    • Figure 32 Typical System Diagram (Generic #2 Bus)

      25
    • Figure 33 Typical System Diagram (Hitachi SH-4 Bus)

      26
    • Figure 34 Typical System Diagram (Hitachi SH-3 Bus)

      27
    • Figure 35 Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000)

      28
    • Figure 36 Typical System Diagram (MC68K #2, Motorola 32-Bit 68030)

      29
    • Figure 37 Typical System Diagram (Motorola REDCAP2 Bus)

      30
    • Figure 38 Typical System Diagram (Motorola MC68EZ328/MC68VZ328 “DragonBall” Bus)

      31
    • Figure 39 Typical System Diagram (Indirect Interface, Mode 68)

      31
    • Figure 310 Typical System Diagram (Indirect Interface, Mode 80)

      32
  • 4 Pins

    33
    • 4.1 Pinout Diagram - PFBGA - 120pin

      33
      • Figure 41 Pinout Diagram - PFBGA 120-pin

        33
      • Table 41: PFBGA 120-pin Mapping

        33
    • 4.2 Pinout Diagram - Die Form

      34
      • Table 42: S1D13708 Pad Layout

        34
    • 4.3 Pin Descriptions

      35
      • 4.3.1 Host Interface

        35
        • Table 43: Host Interface Pin Descriptions

          35
      • 4.3.2 LCD Interface

        40
        • Table 44: LCD Interface Pin Descriptions

          40
      • 4.3.3 Clock Input

        43
        • Table 45: Clock Input Pin Descriptions

          43
      • 4.3.4 Miscellaneous

        43
        • Table 46: Miscellaneous Pin Descriptions

          43
      • 4.3.5 Power And Ground

        43
        • Table 47: Power And Ground Pin Descriptions

          43
    • 4.4 Summary of Configuration Options

      44
      • Table 48: Summary of Power-On/Reset Options

        44
    • 4.5 Host Bus Interface Pin Mapping

      45
      • Table 49: Host Bus Interface Pin Mapping

        45
    • 4.6 LCD Interface Pin Mapping

      46
      • Table 410: LCD Interface Pin Mapping

        46
  • 5 D.C. Characteristics

    47
    • Table 51: Absolute Maximum Ratings (Preliminary - Subject to Change)

      47
    • Table 52: Recommended Operating Conditions

      47
    • Table 53: Electrical Characteristics for VDD = 3.3V typical

      47
  • 6 A.C. Characteristics

    48
    • 6.1 Clock Timing

      48
      • 6.1.1 Input Clocks

        48
        • Figure 61 Clock Input Requirements

          48
        • Table 61: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1

          48
        • Table 62: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1

          49
        • Table 63: Clock Input Requirements for CLKI2

          49
      • 6.1.2 Internal Clocks

        49
        • Table 64: Internal Clock Requirements

          49
    • 6.2 CPU Interface Timing

      50
      • 6.2.1 Generic #1 Interface Timing

        50
        • Figure 62 Generic #1 Interface Timing

          50
        • Table 65: Generic #1 Interface Timing

          51
      • 6.2.2 Generic #2 Interface Timing

        52
        • Figure 63 Generic #2 Interface Timing

          52
        • Table 66: Generic #2 Interface Timing

          53
      • 6.2.3 Hitachi SH-4 Interface Timing

        54
        • Figure 64 Hitachi SH-4 Interface Timing

          54
        • Table 67: Hitachi SH-4 Interface Timing

          55
      • 6.2.4 Hitachi SH-3 Interface Timing

        56
        • Figure 65 Hitachi SH-3 Interface Timing

          56
        • Table 68: Hitachi SH-3 Interface Timing

          57
      • 6.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000)

        58
        • Figure 66 Motorola MC68K #1 Interface Timing

          58
        • Table 69: Motorola MC68K #1 Interface Timing

          59
      • 6.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030)

        60
        • Figure 67 Motorola MC68K #2 Interface Timing

          60
        • Table 610: Motorola MC68K #2 Interface Timing

          61
      • 6.2.7 Motorola REDCAP2 Interface Timing

        62
        • Figure 68 Motorola REDCAP2 Interface Timing

          62
        • Table 611: Motorola REDCAP2 Interface Timing

          63
      • 6.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328)

        64
        • Figure 69 Motorola DragonBall Interface with DTACK Timing

          64
        • Table 612: Motorola DragonBall Interface with DTACK Timing

          65
      • 6.2.9 Motorola DragonBall Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328)

        66
        • Figure 610 Motorola DragonBall Interface without DTACK# Timing

          66
        • Table 613: Motorola DragonBall Interface without DTACK Timing

          67
      • 6.2.10 Indirect Interface Timing (Mode 68)

        68
        • Figure 611 Indirect Interface Timing (Mode 68)

          68
        • Table 614: Indirect Interface Timing (Mode 68)

          69
      • 6.2.11 Indirect Interface Timing (Mode 80)

        70
        • Figure 612 Indirect Interface Timing (Mode 80)

          70
        • Table 615: Indirect Interface Timing (Mode 80)

          71
    • 6.3 LCD Power Sequencing

      72
      • 6.3.1 Passive/TFT Power-On Sequence

        72
        • Figure 613 Passive/TFT Power-On Sequence Timing

          72
        • Table 616: Passive/TFT Power-On Sequence Timing

          72
      • 6.3.2 Passive/TFT Power-Off Sequence

        73
        • Figure 614 Passive/TFT Power-Off Sequence Timing

          73
        • Table 617: Passive/TFT Power-Off Sequence Timing

          73
    • 6.4 Display Interface

      74
      • Figure 615 Panel Timing Parameters

        74
      • Table 618: Panel Timing Parameter Definition and Register Summary

        75
      • 6.4.1 Generic STN Panel Timing

        76
        • Figure 616 Generic STN Panel Timing

          76
      • 6.4.2 Single Monochrome 4-Bit Panel Timing

        78
        • Figure 617 Single Monochrome 4-Bit Panel Timing

          78
        • Figure 618 Single Monochrome 4-Bit Panel A.C. Timing

          79
        • Table 619: Single Monochrome 4-Bit Panel A.C. Timing

          79
      • 6.4.3 Single Monochrome 8-Bit Panel Timing

        80
        • Figure 619 Single Monochrome 8-Bit Panel Timing

          80
        • Figure 620 Single Monochrome 8-Bit Panel A.C. Timing

          81
        • Table 620: Single Monochrome 8-Bit Panel A.C. Timing

          81
      • 6.4.4 Single Color 4-Bit Panel Timing

        82
        • Figure 621 Single Color 4-Bit Panel Timing

          82
        • Figure 622 Single Color 4-Bit Panel A.C. Timing

          83
        • Table 621: Single Color 4-Bit Panel A.C. Timing

          83
      • 6.4.5 Single Color 8-Bit Panel Timing (Format 1)

        84
        • Figure 623 Single Color 8-Bit Panel Timing (Format 1)

          84
        • Figure 624 Single Color 8-Bit Panel A.C. Timing (Format 1)

          85
        • Table 622: Single Color 8-Bit Panel A.C. Timing (Format 1)

          85
      • 6.4.6 Single Color 8-Bit Panel Timing (Format 2)

        86
        • Figure 625 Single Color 8-Bit Panel Timing (Format 2)

          86
        • Figure 626 Single Color 8-Bit Panel A.C. Timing (Format 2)

          87
        • Table 623: Single Color 8-Bit Panel A.C. Timing (Format 2)

          87
      • 6.4.7 Single Color 16-Bit Panel Timing

        88
        • Figure 627 Single Color 16-Bit Panel Timing

          88
        • Figure 628 Single Color 16-Bit Panel A.C. Timing

          89
        • Table 624: Single Color 16-Bit Panel A.C. Timing

          89
      • 6.4.8 Generic TFT Panel Timing

        90
        • Figure 629 Generic TFT Panel Timing

          90
      • 6.4.9 9/12/18-Bit TFT Panel Timing

        91
        • Figure 630 18-Bit TFT Panel Timing

          91
        • Figure 631 TFT A.C. Timing

          92
        • Table 625: TFT A.C. Timing

          93
      • 6.4.10 160x160 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ031B1DDxx)

        94
        • Figure 632 160x160 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing

          94
        • Table 626: 160x160 Sharp ‘Direct’ HR-TFT Horizontal Timing

          95
        • Figure 633 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing

          96
        • Table 627: 160x160 Sharp ‘Direct’ HR-TFT Panel Vertical Timing

          97
      • 6.4.11 320x240 Sharp ‘Direct’ HR-TFT Panel Timing (e.g. LQ039Q2DS01)

        98
        • Figure 634 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing

          98
        • Table 628: 320x240 Sharp ‘Direct’ HR-TFT Panel Horizontal Timing

          99
        • Figure 635 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing

          99
        • Table 629: 320x240 Sharp ‘Direct’ HR-TFT Panel Vertical Timing

          99
      • 6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR)

        100
        • Figure 636 160x240 Epson D-TFD Panel Horizontal Timing

          100
        • Table 630: 160x240 Epson D-TFD Panel Horizontal Timing

          101
        • Figure 637 160x240 Epson D-TFD Panel GCP Horizontal Timing

          102
        • Table 631: 160x240 Epson D-TFD Panel GCP Horizontal Timing

          102
        • Figure 638 160x240 Epson D-TFD Panel Vertical Timing

          103
        • Table 632: 160x240 Epson D-TFD Panel Vertical Timing

          103
      • 6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR)

        104
        • Figure 639 320x240 Epson D-TFD Panel Horizontal Timing

          104
        • Table 633: 320x240 Epson D-TFD Panel Horizontal Timing

          105
        • Figure 640 320x240 Epson D-TFD Panel GCP Horizontal Timing

          106
        • Table 634: 320x240 Epson D-TFD Panel GCP Horizontal Timing

          106
        • Figure 641 320x240 Epson D-TFD Panel Vertical Timing

          107
        • Table 635: 320x240 Epson D-TFD Panel Vertical Timing

          107
      • 6.4.14 TFT Type 2 Panel Timing

        108
        • Figure 642 TFT Type 2 Horizontal Timing

          108
        • Table 636: TFT Type 2 Horizontal Timing

          109
        • Figure 643 TFT Type 2 Vertical Timing

          110
        • Table 637: TFT Type 2 Vertical Timing

          110
      • 6.4.15 TFT Type 3 Panel Timing

        111
        • Figure 644 TFT Type 3 Horizontal Timing

          111
        • Table 638: TFT Type 3 Horizontal Timing

          112
        • Figure 645 TFT Type 3 Vertical Timing

          113
        • Table 639: TFT Type 3 Vertical Timing

          114
      • 6.4.16 TFT Type 4 Panel Timing

        115
        • Figure 646 TFT Type 4 Panel Timing

          115
        • Figure 647 TFT Type 4 A.C. Timing

          116
        • Table 640: TFT Type 4 A.C. Timing

          117
  • 7 Clocks

    118
    • 7.1 Clock Descriptions

      118
      • 7.1.1 BCLK

        118
        • Table 71: BCLK Clock Selection

          118
      • 7.1.2 MCLK

        118
        • Table 72: MCLK Clock Selection

          119
      • 7.1.3 PCLK

        119
        • Table 73: PCLK Clock Selection 

          119
        • Table 74: Relationship between MCLK and PCLK

          121
      • 7.1.4 PWMCLK

        121
        • Table 75: PWMCLK Clock Selection

          121
    • 7.2 Clock Selection

      122
      • Figure 71 Clock Selection

        122
    • 7.3 Clocks versus Functions

      123
      • Table 76: S1D13708 Internal Clock Requirements

        123
  • 8 Registers

    124
    • 8.1 Register Mapping

      124
    • 8.2 Register Set

      125
      • Table 81: S1D13708 Register Set

        125
    • 8.3 Register Descriptions

      127
      • 8.3.1 Read-Only Configuration Registers

        127
      • 8.3.2 Clock Configuration Registers

        128
        • Table 82: MCLK Divide Selection

          128
        • Table 83: PCLK Divide Selection

          128
        • Table 84: PCLK Source Selection

          129
      • 8.3.3 Look-Up Table Registers

        129
      • 8.3.4 Panel Configuration Registers

        132
        • Table 85: Panel Data Width Selection

          132
        • Table 86: HRTFT/D-TFD Panel Resolution Selection

          132
        • Table 87: LCD Panel Type Selection

          133
      • 8.3.5 Display Mode Registers

        139
        • Table 88: Inverse Video Mode Select Options

          140
        • Table 89: LCD Bit-per-pixel Selection

          141
        • Figure 81 Display Data Byte/Word Swap

          142
        • Table 810: SwivelViewTM Mode Select Options

          142
      • 8.3.6 Picture-in-Picture Plus Registers

        144
        • Table 811: 32-bit Address Increments for Color Depth

          145
        • Table 812: 32-bit Address Increments for Color Depth

          146
        • Table 813: 32-bit Address Increments for Color Depth

          147
        • Table 814: 32-bit Address Increments for Color Depth

          148
      • 8.3.7 Miscellaneous Registers

        149
      • 8.3.8 General IO Pins Registers

        151
      • 8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers

        156
        • Figure 82 PWM Clock/CV Pulse Block Diagram

          156
        • Table 815: PWM Clock Control

          156
        • Table 816: CV Pulse Control

          157
        • Table 817: PWM Clock Divide Select Options

          158
        • Table 818: CV Pulse Divide Select Options

          158
        • Table 819: PWMOUT Duty Cycle Select Options

          159
      • 8.3.10 Extended Registers

        160
        • Table 820: Extended Panel Type Selection

          161
        • Table 821: VCLK Hold

          165
        • Table 822: VCLK Setup

          165
        • Table 823: AP Pulse Width

          166
        • Table 824: AP Rising Position

          166
        • Table 825: GPO2 PCLK2 Divide Rate

          170
        • Table 826: GPO1 PCLK1 Divide Rate

          170
        • Table 827: Number of Source Driver ICs

          176
  • 9 Frame Rate Calculation

    177
  • 10 Display Data Formats

    178
    • Figure 101 4/8/16 Bit-Per-Pixel Display Data Memory Organization

      178
  • 11 Look-Up Table Architecture

    179
    • 11.1 Monochrome Modes

      179
      • 1 Bit-per-pixel Monochrome Mode

        179
        • Figure 111 1 Bit-per-pixel Monochrome Mode Data Output Path

          179
      • 2 Bit-per-pixel Monochrome Mode

        179
        • Figure 112 2 Bit-per-pixel Monochrome Mode Data Output Path

          179
      • 4 Bit-per-pixel Monochrome Mode

        180
        • Figure 113 4 Bit-per-pixel Monochrome Mode Data Output Path

          180
      • 8 Bit-per-pixel Monochrome Mode

        180
        • Figure 114 8 Bit-per-pixel Monochrome Mode Data Output Path

          180
      • 16 Bit-Per-Pixel Monochrome Mode

        181
    • 11.2 Color Modes

      181
      • 1 Bit-Per-Pixel Color

        181
        • Figure 115 1 Bit-Per-Pixel Color Mode Data Output Path

          181
      • 2 Bit-Per-Pixel Color

        182
        • Figure 116 2 Bit-Per-Pixel Color Mode Data Output Path

          182
      • 4 Bit-Per-Pixel Color

        183
        • Figure 117 4 Bit-Per-Pixel Color Mode Data Output Path

          183
      • 8 Bit-per-pixel Color Mode

        184
        • Figure 118 8 Bit-per-pixel Color Mode Data Output Path

          184
      • 16 Bit-Per-Pixel Color Mode

        184
  • 12 SwivelView™

    185
    • 12.1 Concept

      185
    • 12.2 90 SwivelView™

      185
      • Figure 121 Relationship Between The Screen Image and the Image Refreshed in 90° SwivelView.

        185
      • 12.2.1 Register Programming

        186
    • 12.3 180 SwivelView™

      187
      • Figure 122 Relationship Between The Screen Image and the Image Refreshed in 180° SwivelView.

        187
      • 12.3.1 Register Programming

        187
    • 12.4 270 SwivelView™

      188
      • Figure 123 Relationship Between The Screen Image and the Image Refreshed in 270° SwivelView.

        188
      • 12.4.1 Register Programming

        189
  • 13 Picture-in-Picture Plus (PIP+)

    190
    • 13.1 Concept

      190
      • Figure 131 Picture-in-Picture Plus with SwivelView disabled

        190
    • 13.2 With SwivelView Enabled

      191
      • 13.2.1 SwivelView 90

        191
        • Figure 132 Picture-in-Picture Plus with SwivelView 90 enabled

          191
      • 13.2.2 SwivelView 180

        191
        • Figure 133 Picture-in-Picture Plus with SwivelView 180 enabled

          191
      • 13.2.3 SwivelView 270

        192
        • Figure 134 Picture-in-Picture Plus with SwivelView 270 enabled

          192
  • 14 Ink Layer

    193
    • 14.1 Memory Mapping

      193
      • Figure 141 Memory Mapping for Ink Layer

        193
    • 14.2 Controlling the Ink Layer

      193
      • Figure 142 Transparent Color Example

        194
    • 14.3 Limitations

      194
  • 15 Indirect Interface

    195
    • 15.1 Mode 68

      196
      • Figure 151 Sample timing of “register write” with Mode 68

        196
      • Figure 152 Sample timing of “register read” with Mode 68

        197
      • Figure 153 Sample timing of “memory write” with Mode 68, Big Endian

        198
      • Figure 154 Sample timing of “memory read” with Mode 68, Big Endian

        200
      • Figure 155 Sample timing of “register write” for Mode 68 when Memory Access Select Enabled

        202
      • Figure 156 Sample timing of “register read” for Mode 68 when Memory Access Select Enabled

        204
    • 15.2 Mode 80

      206
      • Figure 157 Sample timing of “register write” with Mode 80

        206
      • Figure 158 Sample timing of “register read” with Mode 80

        208
      • Figure 159 Sample timing of “memory write” with mode 80, little endian

        209
      • Figure 1510 Sample timing of “memory read” with mode 80, Little endian

        211
      • Figure 1511 Sample timing of “memory write” for Mode 80 when Memory Access Select Enabled

        213
      • Figure 1512 Sample timing of “memory read” for Mode 80 when Memory Access Select Enabled

        215
    • 15.3 Limitations

      216
  • 16 Embedded Crystal Oscillator

    217
    • 16.1 Oscillator Circuit

      217
      • Figure 161 Recommended Crystal Oscillator Circuit

        217
  • 17 Big-Endian Bus Interface

    218
    • 17.1 Byte Swapping Bus Data

      218
      • 17.1.1 16 Bpp Color Depth

        219
        • Figure 171 Byte-swapping for 16 Bpp

          219
      • 17.1.2 1/2/4/8 Bpp Color Depth

        220
        • Figure 172 Byte-swapping for 1/2/4/8 Bpp

          220
  • 18 Power Save Mode

    221
    • Table 181: Power Save Mode Function Summary

      221
  • 19 Mechanical Data

    222
    • Figure 191 Mechanical Data PFBGA 120-pin Package

      222
  • 20 References

    223
  • 21 Technical Support

    224
• S1D13708 Embedded Memory LCD Controller

  225
  • Table of Contents

    227
  • List of Tables

    229
  • List of Figures

    231
  • 1 Introduction

    233
  • 2 Identifying the S1D13708

    234
  • 3 Initialization

    235
  • 4 Memory Models

    236
    • 4.1 Memory Organization for One Bit-per-pixel (2 Colors/Gray Shades)

      236
      • Figure 41: Pixel Storage for 1 Bpp in One Byte of Display Buffer

        236
    • 4.2 Memory Organization for Two Bit-per-pixel (4 Colors/Gray Shades)

      236
      • Figure 42: Pixel Storage for 2 Bpp in One Byte of Display Buffer

        236
    • 4.3 Memory Organization for Four Bit-per-pixel (16 Colors/Gray Shades)

      237
      • Figure 43: Pixel Storage for 4 Bpp in One Byte of Display Buffer

        237
    • 4.4 Memory Organization for 8 Bpp (256 Colors/64 Gray Shades)

      237
      • Figure 44: Pixel Storage for 8 Bpp in One Byte of Display Buffer

        237
    • 4.5 Memory Organization for 16 Bpp (65536 Colors/64 Gray Shades)

      238
      • Figure 45: Pixel Storage for 16 Bpp in Two Bytes of Display Buffer

        238
  • 5 Look-Up Table (LUT)

    239
    • 5.1 Registers

      239
      • 5.1.1 Look-Up Table Registers

        239
    • 5.2 Look-Up Table Organization

      242
      • Table 51: Look-Up Table Configurations

        242
      • 5.2.1 Gray Shade Modes

        243
        • Table 52: Suggested LUT Values for 1 Bpp Gray Shade

          243
        • Table 53: Suggested LUT Values for 4 Bpp Gray Shade

          243
        • Table 54: Suggested LUT Values for 4 Bpp Gray Shade

          244
        • Table 55: Suggested LUT Values for 8 Bpp Gray Shade

          245
      • 5.2.2 Color Modes

        247
        • Table 56: Suggested LUT Values for 1 bpp Color

          247
        • Table 57: Suggested LUT Values for 2 bpp Color

          247
        • Table 58: Suggested LUT Values for 4 bpp Color

          248
        • Table 59: Suggested LUT Values for 8 bpp Color

          249
  • 6 Power Save Mode

    251
    • 6.1 Overview

      251
    • 6.2 Registers

      252
      • 6.2.1 Power Save Mode Enable

        252
      • 6.2.2 Memory Controller Power Save Status

        252
    • 6.3 LCD Power Sequencing

      253
    • 6.4 Enabling Power Save Mode

      254
    • 6.5 Disabling Power Save Mode

      254
  • 7 SwivelView‘

    255
    • 7.1 SwivelView Registers

      255
      • Table 71: SwivelViewTM Mode Select Options

        255
    • 7.2 Examples

      257
    • 7.3 Limitations

      261
      • 7.3.1 SwivelView 0 and 180

        261
      • 7.3.2 SwivelView 90 and 270

        261
  • 8 Picture-In-Picture Plus

    262
    • 8.1 Concept

      262
      • Figure 81: Picture-in-Picture Plus with SwivelView disabled

        262
    • 8.2 Registers

      262
      • Table 81: 32-bit Address Increments for Color Depth

        265
      • Table 82: 32-bit Address Increments for Color Depth

        267
      • Table 83: 32-bit Address Increments for Color Depth

        269
      • Table 84: 32-bit Address Increments for Color Depth

        270
    • 8.3 Picture-In-Picture-Plus Examples

      272
      • 8.3.1 SwivelView 0 (Landscape Mode)

        272
        • Figure 82: Picture-in-Picture Plus with SwivelView disabled

          272
      • 8.3.2 SwivelView 90

        275
        • Figure 83: Picture-in-Picture Plus with SwivelView 90 enabled

          275
      • 8.3.3 SwivelView 180

        278
        • Figure 84: Picture-in-Picture Plus with SwivelView 180 enabled

          278
      • 8.3.4 SwivelView 270

        282
        • Figure 85: Picture-in-Picture Plus with SwivelView 270 enabled

          282
    • 8.4 Limitations

      286
      • 8.4.1 SwivelView 0 and 180

        286
      • 8.4.2 SwivelView 90 and 270

        286
  • 9 Hardware Abstraction Layer

    287
    • 9.1 Introduction

      287
    • 9.2 API for the HAL Library

      287
      • Table 91: HAL Library API

        287
      • 9.2.1 Startup Routines

        288
      • 9.2.2 Memory Access

        290
      • 9.2.3 Register Access

        291
      • 9.2.4 Clock Support

        293
      • 9.2.5 Miscellaneous

        294
  • 10 Sample Code

    296
  • 11 Sales and Technical Support

    297
• S1D13708 Register Summary X39A-R-001-01

  299
• 13708CFG Configuration Program

  303
  • Table of Contents

    305
  • 13708CFG

    307
    • S1D13708 Supported Evaluation Platforms

      307
    • Installation

      307
    • Usage

      307
    • 13708CFG Configuration Tabs

      308
      • General Tab

        308
      • Preferences Tab

        310
      • Clocks Tab

        311
      • Panel Tab

        316
      • Panel Power Tab

        320
      • Registers Tab

        321
    • 13708CFG Menus

      322
      • Open...

        322
      • Save

        323
      • Save As...

        323
      • Configure Multiple

        323
      • Export

        325
      • Enable Tooltips

        326
      • ERD on the Web

        326
      • About 13708CFG

        326
    • Comments

      326
• 13708PLAY Diagnostic Utility

  327
  • 13708PLAY

    329
    • S1D13708 Supported Evaluation Platforms

      329
    • Installation

      330
    • Usage

      330
    • Commands

      331
    • 13708PLAY Example

      337
    • Script Files

      338
• 13708BMP Demonstration Program

  339
  • 13708BMP

    341
    • S1D13708 Supported Evaluation Platforms

      341
    • Installation

      341
    • Usage

      342
    • 13708BMP Examples

      342
    • Comments

      342
• Wind River WindML v2.0 Display Drivers

  343
  • Wind River WindML v2.0 DISPLAY DRIVERS

    345
    • Building a WindML v2.0 Display Driver

      346
      • 1. Create a working directory and unzip the WindML display driver into it.

        346
      • 2. Configure for the target execution model.

        346
      • 3. Build a boot ROM image.

        346
      • 4. Create a bootable disk (in drive A:).

        346
      • 5. If necessary, generate a new mode0.h configuration file.

        346
      • 6. Build the WindML v2.0 library.

        347
      • 7. Open the S1D13708 workspace.

        347
      • 8. Add support for single line comments.

        347
        • a. In the Tornado “Workspace Views” window, click on the “Builds” tab.

          347
        • b. Expand the “8bpp Builds” (or “16bpp Builds”) view by clicking on the “+” next to it. The expan...

          347
        • c. Select the “C/C++ compiler” tab to display the command switches used in the build. Remove the ...

          347
      • 9. Compile the VxWorks image.

        347
      • 10. Copy the VxWorks file to the diskette.

        347
      • 11. Start the VxWorks demo.

        347
• Linux Console Driver

  349
  • Linux Console Driver

    351
    • Building the Console Driver for Linux Kernel 2.2.x

      352
      • 1. Acquire the Linux kernel source code.

        352
      • 2. Unzip the console driver files.

        352
      • 3. Copy the console driver files to the build directory.

        352
      • 4. Modify s1d13708.h

        353
      • 5. Configure the video options.

        353
      • 6. Compile and install the kernel.

        353
      • 7. Boot to the Linux operating system.

        354
    • Building the Console Driver for Linux Kernel 2.4.x

      355
      • 1. Acquire the Linux kernel source code.

        355
      • 2. Unzip the console driver files.

        355
      • 3. Copy the console driver files to the build directory. Make the directory /usr/src/linux/driver...

        355
      • 4. Modify s1d13708.h

        356
      • 5. Configure the video options.

        356
      • 6. Compile and install the kernel

        357
      • 7. Boot to the Linux operating system

        357
• QNX Photon v2.0 Display Driver

  359
  • QNX Photon v2.0 Display Driver

    361
    • Building the Photon v2.0 Display Driver

      362
      • Unpack the Graphics Driver Development Kit Archive

        362
      • Configure the Driver

        362
      • Build the Driver

        362
      • Installing the Driver

        363
      • Run the Driver

        363
    • Comments

      364
• Windows® CE 3.x Display Drivers

  365
  • WINDOWS® CE 3.0 DISPLAY DRIVER

    367
    • Example Driver Builds

      368
    • Installation for CEPC Environment

      372
    • Configuration

      373
      • Compile Switches

        373
      • Mode File

        374
      • Resource Management Issues

        375
    • Comments

      378
• Power Consumption

  379
  • 1 S1D13708 Power Consumption

    381
    • 1.1 Conditions

      382
      • Table 11: S1D13708 Power Consumption

        382
  • 2 Summary

    383
• Interfacing to the NEC VR4102 / VR4111 Microprocessors

  385
  • Table of Contents

    387
  • List of Tables

    389
  • List of Figures

    389
  • 1 Introduction

    391
  • 2 Interfacing to the NEC VR4102/VR4111

    392
    • 2.1 The NEC VR41XX System Bus

      392
      • 2.1.1 Overview

        392
      • 2.1.2 LCD Memory Access Cycles

        393
        • Figure 21: NEC VR4102/VR4111 Read/Write Cycles

          393
  • 3 S1D13708 Host Bus Interface

    394
    • 3.1 Host Bus Interface Pin Mapping

      394
      • Table 31: Host Bus Interface Pin Mapping

        394
    • 3.2 Host Bus Interface Signals

      395
  • 4 VR4102/VR4111 to S1D13708 Interface

    396
    • 4.1 Hardware Description

      396
      • Figure 41: Typical Implementation of VR4102/VR4111 to S1D13708 Interface

        396
    • 4.2 S1D13708 Hardware Configuration

      397
      • Table 41: Summary of Power-On/Reset Configuration Options

        397
      • Table 42: CLKI to BCLK Divide Selection

        397
    • 4.3 NEC VR4102/VR4111 Configuration

      398
  • 5 Software

    399
  • 6 References

    400
    • 6.1 Documents

      400
    • 6.2 Document Sources

      400
  • 7 Technical Support

    401
    • 7.1 Epson LCD Controllers (S1D13708)

      401
    • 7.2 NEC Electronics Inc.

      401
• Interfacing to the NEC VR4181A™ Microprocessor

  403
  • Table of Contents

    405
  • List of Tables

    407
  • List of Figures

    407
  • 1 Introduction

    409
  • 2 Interfacing to the NEC VR4181A

    410
    • 2.1 The NEC VR4181A System Bus

      410
      • 2.1.1 Overview

        410
      • 2.1.2 LCD Memory Access Signals

        411
  • 3 S1D13708 Host Bus Interface

    412
    • 3.1 Host Bus Interface Pin Mapping

      412
      • Table 31: Host Bus Interface Pin Mapping

        412
    • 3.2 Host Bus Interface Signals

      413
  • 4 VR4181A to S1D13708 Interface

    414
    • 4.1 Hardware Description

      414
      • Figure 41: Typical Implementation of VR4181A to S1D13708 Interface

        414
    • 4.2 S1D13708 Hardware Configuration

      415
      • Table 41: Summary of Power-On/Reset Configuration Options

        415
      • Table 42: CLKI to BCLK Divide Selection

        415
    • 4.3 NEC VR4181A Configuration

      416
  • 5 Software

    417
  • 6 References

    418
    • 6.1 Documents

      418
    • 6.2 Document Sources

      418
  • 7 Technical Support

    419
    • 7.1 Epson LCD Controllers (S1D13708)

      419
    • 7.2 NEC Electronics Inc.

      419
• Interfacing to the Motorola MPC821 Microprocessor

  421
  • Document Number: X39A-G-009-01

    421
  • Table of Contents

    423
  • List of Tables

    425
  • List of Figures

    425
  • 1 Introduction

    427
  • 2 Interfacing to the MPC821

    428
    • 2.1 The MPC8XX System Bus

      428
    • 2.2 MPC8XX Bus Overview

      428
      • 2.2.1 Normal (Non-Burst) Bus Transactions

        429
        • Figure 21: Power PC Memory Read Cycle

          429
        • Figure 22: Power PC Memory Write Cycle

          430
      • 2.2.2 Burst Cycles

        430
    • 2.3 Memory Controller Module

      431
      • 2.3.1 General-Purpose Chip Select Module (GPCM)

        431
        • Figure 23: GPCM Memory Devices Timing

          432
      • 2.3.2 User-Programmable Machine (UPM)

        432
  • 3 S1D13708 Host Bus Interface

    433
    • 3.1 Host Bus Interface Pin Mapping

      433
      • Table 31: Host Bus Interface Pin Mapping

        433
    • 3.2 Host Bus Interface Signals

      434
  • 4 MPC821 to S1D13708 Interface

    435
    • 4.1 Hardware Description

      435
      • Figure 41: Typical Implementation of MPC821 to S1D13708 Interface

        435
    • 4.2 MPC821ADS Evaluation Board Hardware Connections

      436
      • Table 41: List of Connections from MPC821ADS to S1D13708 

        436
    • 4.3 S1D13708 Hardware Configuration

      438
      • Table 42: Summary of Power-On/Reset Configuration Options

        438
      • Table 43: CLKI to BCLK Divide Selection

        438
    • 4.4 Register/Memory Mapping

      438
    • 4.5 MPC821 Chip Select Configuration

      439
    • 4.6 Test Software

      440
  • 5 Software

    441
  • 6 References

    442
    • 6.1 Documents

      442
    • 6.2 Document Sources

      442
  • 7 Technical Support

    443
    • 7.1 EPSON LCD/CRT Controllers (S1D13708)

      443
    • 7.2 Motorola MPC821 Processor

      443
• Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor

  445
  • Table of Contents

    447
  • List of Tables

    449
  • List of Figures

    449
  • 1 Introduction

    451
  • 2 Interfacing to the MCF5307

    452
    • 2.1 The MCF5307 System Bus

      452
      • 2.1.1 Overview

        452
      • 2.1.2 Normal (Non-Burst) Bus Transactions

        452
        • Figure 21: MCF5307 Memory Read Cycle

          453
        • Figure 22: MCF5307 Memory Write Cycle

          453
      • 2.1.3 Burst Cycles

        453
    • 2.2 Chip-Select Module

      454
      • Figure 23: Chip Select Module Outputs Timing

        454
  • 3 S1D13708 Host Bus Interface

    455
    • 3.1 Host Bus Interface Pin Mapping

      455
      • Table 31: Host Bus Interface Pin Mapping

        455
    • 3.2 Host Bus Interface Signals

      456
  • 4 MCF5307 To S1D13708 Interface

    457
    • 4.1 Hardware Description

      457
      • Figure 41: Typical Implementation of MCF5307 to S1D13708 Interface

        457
    • 4.2 S1D13708 Hardware Configuration

      458
      • Table 41: Summary of Power-On/Reset Configuration Options

        458
      • Table 42: CLKI to BCLK Divide Selection

        458
    • 4.3 Register/Memory Mapping

      459
    • 4.4 MCF5307 Chip Select Configuration

      459
  • 5 Software

    460
  • 6 References

    461
    • 6.1 Documents

      461
    • 6.2 Document Sources

      461
  • 7 Technical Support

    462
    • 7.1 EPSON LCD Controllers (S1D13708)

      462
    • 7.2 Motorola MCF5307 Processor

      462
• Connecting to the Sharp HR-TFT Panels

  463
  • Table of Contents

    465
  • List of Tables

    467
  • List of Figures

    467
  • 1 Introduction

    469
  • 2 Connecting to the Sharp LQ039Q2DS01 HR-TFT

    470
    • 2.1 External Power Supplies

      470
      • 2.1.1 Gray Scale Voltages for Gamma Correction

        470
        • Figure 21: Sharp LQ039Q2DS01 Gray Scale Voltage (V0-V9) Generation

          470
      • 2.1.2 Digital/Analog Power Supplies

        471
      • 2.1.3 DC Gate Driver Power Supplies

        471
        • Figure 22: Panel Gate Driver DC Power Supplies

          471
      • 2.1.4 AC Gate Driver Power Supplies

        472
        • Figure 23: Panel Gate Driver AC Power Supplies

          472
    • 2.2 HR-TFT MOD Signal

      473
      • Figure 24: HR-TFT Power-On/Off Sequence Timing

        473
      • Table 21: HR-TFT Power-On/Off Sequence Timing

        473
    • 2.3 S1D13708 to LQ039Q2DS01 Pin Mapping

      474
      • Table 22: S1D13708 to LQ039Q2DS01 Pin Mapping

        474
  • 3 Connecting to the Sharp LQ031B1DDxx HR-TFT

    476
    • 3.1 External Power Supplies

      476
      • 3.1.1 Gray Scale Voltages for Gamma Correction

        476
        • Figure 31: Sharp LQ031B1DDxx Gray Scale Voltage (V0-V9) Generation

          476
      • 3.1.2 Digital/Analog Power Supplies

        477
      • 3.1.3 DC Gate Driver Power Supplies

        477
      • 3.1.4 AC Gate Driver Power Supplies

        477
    • 3.2 HR-TFT MOD Signal

      477
    • 3.3 S1D13708 to LQ031B1DDxx Pin Mapping

      478
      • Table 31: S1D13708 to LQ031B1DDxx Pin Mapping

        478
  • 4 Test Software

    480
  • 5 References

    481
    • 5.1 Documents

      481
    • 5.2 Document Sources

      481
  • 6 Technical Support

    482
    • 6.1 EPSON LCD Controllers (S1D13708)

      482
    • 6.2 Sharp HR-TFT Panel

      482
• Interfacing to the Motorola RedCap2

  483
  • Table of Contents

    485
  • List of Tables

    487
  • List of Figures

    487
  • 1 Introduction

    489
  • 2 Interfacing to the REDCAP2

    490
    • 2.1 The REDCAP2 System Bus

      490
    • 2.2 Overview

      490
    • 2.3 Bus Transactions

      490
      • Figure 21: REDCAP2 Memory Read Cycle

        491
      • Figure 22: REDCAP2 Memory Write Cycle

        491
  • 3 S1D13708 Host Bus Interface

    492
    • 3.1 Host Bus Interface Pin Mapping

      492
      • Table 31: Host Bus Interface Pin Mapping

        492
    • 3.2 Host Bus Interface Signals

      493
  • 4 REDCAP2 to S1D13708 Interface

    494
    • 4.1 Hardware Description

      494
      • Figure 41: Typical Implementation of REDCAP2 to S1D13708 Interface

        494
    • 4.2 Hardware Connections

      495
      • Table 41: List of Connections for REDCAP2 ADM

        495
    • 4.3 S1D13708 Hardware Configuration

      497
      • Table 42: Summary of Power-On/Reset Options

        497
    • 4.4 Register/Memory Mapping

      497
    • 4.5 REDCAP2 Chip Select Configuration

      498
  • 5 Software

    499
  • 6 References

    500
    • 6.1 Documents

      500
    • 6.2 Document Sources

      500
  • 7 Technical Support

    501
    • 7.1 EPSON LCD/CRT Controllers (S1D13708)

      501
    • 7.2 Motorola REDCAP2 Processor

      501
• Interfacing to 8-bit Processors

  503
  • Table of Contents

    505
  • List of Tables

    507
  • List of Figures

    507
  • 1 Introduction

    509
  • 2 Interfacing to an 8-bit Processor

    510
    • 2.1 The Generic 8-bit Processor System Bus

      510
  • 3 S1D13708 Host Bus Interface

    511
    • 3.1 Host Bus Interface Pin Mapping

      511
      • Table 31: Host Bus Interface Pin Mapping

        511
    • 3.2 Host Bus Interface Signals

      512
  • 4 8-Bit Processor to S1D13708 Interface

    513
    • 4.1 Hardware Connections

      513
      • Figure 41: Typical Implementation of 8-bit Processor to S1D13708 Interface

        513
    • 4.2 S1D13708 Hardware Configuration

      514
      • Table 41: Summary of Power-On/Reset Configuration Options

        514
      • Table 42: CLKI to BCLK Divide Selection

        514
    • 4.3 Register/Memory Mapping

      514
  • 5 Software

    515
  • 6 References

    516
    • 6.1 Documents

      516
    • 6.2 Document Sources

      516
  • 7 Technical Support

    517
    • 7.1 EPSON LCD Controllers (S1D13708)

      517
• Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor

  519
  • Document Number: X39A-G-016-01

    519
  • Table of Contents

    521
  • List of Tables

    523
  • List of Figures

    523
  • 1 Introduction

    525
  • 2 Interfacing to the MC68VZ328

    526
    • 2.1 The MC68VZ328 System Bus

      526
    • 2.2 Chip-Select Module

      526
  • 3 S1D13708 Host Bus Interface

    527
    • 3.1 Host Bus Interface Pin Mapping

      527
      • Table 31: Host Bus Interface Pin Mapping

        527
    • 3.2 Host Bus Interface Signals

      528
  • 4 MC68VZ328 to S1D13708 Interface

    529
    • 4.1 Hardware Description

      529
      • Figure 41: Typical Implementation of MC68VZ328 to S1D13708 Interface

        529
    • 4.2 S1D13708 Hardware Configuration

      530
      • Table 41: Summary of Power-On/Reset Configuration Options

        530
      • Table 42: CLKI to BCLK Divide Selection

        530
      • 4.2.1 Register/Memory Mapping

        531
      • 4.2.2 MC68VZ328 Chip Select and Pin Configuration

        531
        • Table 43: WS Bit Programming

          531
  • 5 Software

    532
  • 6 References

    533
    • 6.1 Documents

      533
    • 6.2 Document Sources

      533
  • 7 Technical Support

    534
    • 7.1 EPSON LCD/CRT Controllers (S1D13708)

      534
    • 7.2 Motorola MC68VZ328 Processor

      534
• Interfacing to the Intel StrongARM SA-1110 Microprocessor

  535
  • Document Number: X39A-G-019-01

    535
  • Table of Contents

    537
  • List of Tables

    539
  • List of Figures

    539
  • 1 Introduction

    541
  • 2 Interfacing to the StrongARM SA-1110 Bus

    542
    • 2.1 The StrongARM SA-1110 System Bus

      542
      • 2.1.1 StrongARM SA-1110 Overview

        542
      • 2.1.2 Variable-Latency IO Access Overview

        542
      • 2.1.3 Variable-Latency IO Access Cycles

        543
        • Figure 21: SA-1110 Variable-Latency IO Read Cycle

          543
        • Figure 22: SA-1110 Variable-Latency IO Write Cycle

          544
  • 3 S1D13708 Host Bus Interface

    545
    • 3.1 Host Bus Interface Pin Mapping

      545
      • Table 31: Host Bus Interface Pin Mapping

        545
    • 3.2 Host Bus Interface Signal Descriptions

      546
  • 4 StrongARM SA-1110 to S1D13708 Interface

    547
    • 4.1 Hardware Description

      547
      • Figure 41: Typical Implementation of SA-1110 to S1D13708 Interface

        547
    • 4.2 S1D13708 Hardware Configuration

      548
      • Table 41: Summary of Power-On/Reset Configuration Options

        548
      • Table 42: CLKI to BCLK Divide Selection

        548
    • 4.3 StrongARM SA-1110 Register Configuration

      549
      • Table 43: RDFx Parameter Value versus CPU Maximum Frequency

        549
    • 4.4 Register/Memory Mapping

      550
  • 5 Software

    551
  • 6 References

    552
    • 6.1 Documents

      552
    • 6.2 Document Sources

      552
  • 7 Technical Support

    553
    • 7.1 EPSON LCD Controllers (S1D13708)

      553
    • 7.2 Intel StrongARM SA-1110 Processor

      553
• Connecting to a Micro-Controller via the Indirect Interface

  555
  • Table of Contents

    557
  • List of Tables

    559
  • List of Figures

    559
  • 1 Introduction

    561
  • 2 Interfacing to a Micro-Controller

    562
    • 2.1 The Indirect Interface

      562
  • 3 S1D13708 Host Bus Interface

    563
    • 3.1 Indirect Mode Bus Interface Pin Mapping

      563
      • Table 31: Mode 68 8-Bit Data Host Bus Interface Pin Mapping

        563
      • Table 32: Mode 68 16-Bit Data Host Bus Interface Pin Mapping

        564
      • Table 33: Mode 80 8-Bit Data Host Bus Interface Pin Mapping

        564
      • Table 34: Mode 80 16-Bit Data Host Bus Interface Pin Mapping

        565
    • 3.2 Host Bus Interface Signals

      566
  • 4 Micro-Controller to S1D13708 Interface

    567
    • 4.1 Hardware Connections

      567
      • Figure 41: Typical Implementation of Micro-Controller to S1D13708 Interface

        567
    • 4.2 S1D13708 Hardware Configuration

      568
      • Table 41: Summary of Power-On/Reset Configuration Options

        568
      • Table 42: CLKI to BCLK Divide Selection

        568
    • 4.3 Register/Memory Mapping

      569
  • 5 Software

    570
  • 6 References

    572
    • 6.1 Documents

      572
    • 6.2 Document Sources

      572
  • 7 Technical Support

    573
    • 7.1 EPSON LCD Controllers (S1D13708)

      573