Benutzerhandbuch für Freescale Semiconductor DSP56364

Inhaltsverzeichnis

• DSP56364 Users Manual

  1
• Contact Information

  2
• Contents

  3
• Preface

  15
• 1 Overview

  19
  • 1.1 Introduction

    19
  • 1.2 Features

    20
  • 1.3 Audio Processor Architecture

    21
  • 1.4 Core Description

    22
  • 1.5 DSP56300 Core Functional Blocks

    22
    • 1.5.1 Data ALU

      22
      • 1.5.1.1 Data ALU Registers

        23
      • 1.5.1.2 Multiplier-Accumulator (MAC)

        23
    • 1.5.2 Address Generation Unit (AGU)

      23
    • 1.5.3 Program Control Unit (PCU)

      24
    • 1.5.4 Internal Buses

      24
    • 1.5.5 Direct Memory Access (DMA)

      25
    • 1.5.6 PLL-based Clock Oscillator

      25
    • 1.5.7 JTAG TAP and OnCE Module

      26
  • 1.6 Data and Program memory

    26
    • 1.6.1 Reserved Memory Spaces

      26
    • 1.6.2 Program ROM Area Reserved for Freescale Use

      26
    • 1.6.3 Bootstrap ROM

      26
    • 1.6.4 Dynamic Memory Configuration Switching

      26
    • 1.6.5 External Memory Support

      27
  • 1.7 Internal I/O Memory Map

    27
  • 1.8 Status Register (SR)

    28
• 2 Signal/Connection Descriptions

  29
  • 2.1 Signal Groupings

    29
  • 2.2 Power

    31
  • 2.3 Ground

    31
  • 2.4 Clock and PLL

    32
  • 2.5 External Memory Expansion Port (Port A)

    32
    • 2.5.1 External Address Bus

      32
    • 2.5.2 External Data Bus

      33
    • 2.5.3 External Bus Control

      33
  • 2.6 Interrupt and Mode Control

    34
  • 2.7 Serial Host Interface

    35
  • 2.8 Enhanced Serial Audio Interface

    38
  • 2.9 JTAG/OnCE Interface

    41
  • 2.10 GPIO Signals

    42
• 3 Memory Configuration

  43
  • 3.1 Memory Spaces

    43
    • 3.1.1 Program Memory Space

      43
      • 3.1.1.1 Program RAM

        43
      • 3.1.1.2 Program ROM

        43
      • 3.1.1.3 Bootstrap ROM

        44
      • 3.1.1.4 Reserved Program Memory Locations

        44
    • 3.1.2 Data Memory Spaces

      44
      • 3.1.2.1 X Data Memory Space

        44
      • 3.1.2.2 X Data RAM

        45
      • 3.1.2.3 Y Data Memory Space

        45
      • 3.1.2.4 Y Data RAM

        45
  • 3.2 Memory Space Configuration

    45
  • 3.3 Internal Memory Configuration

    45
    • 3.3.1 RAM Locations

      46
    • 3.3.2 ROM Locations

      46
    • 3.3.3 Dynamic Memory Configuration Switching

      47
  • 3.4 Memory Maps

    48
  • 3.5 External Memory Support

    50
  • 3.6 Internal I/O Memory Map

    50
• 4 Core Configuration

  51
  • 4.1 Introduction

    51
  • 4.2 Operating Mode Register (OMR)

    51
    • 4.2.1 Mode C (MC) - Bit 2

      52
    • 4.2.2 Address Attribute Priority Disable (APD) - Bit 14

      52
    • 4.2.3 Address Tracing Enable (ATE) - Bit 15

      52
  • 4.3 Operating Modes

    53
  • 4.4 Bootstrap Program

    54
  • 4.5 Interrupt Priority Registers

    54
  • 4.6 DMA Request Sources

    57
  • 4.7 PLL and Clock Generator

    57
    • 4.7.1 PLL Multiplication Factor (MF0-MF11) - Bits 0-11

      57
    • 4.7.2 Crystal Range Bit (XTLR) - Bit 15

      58
    • 4.7.3 XTAL Disable Bit (XTLD) - Bit 16

      58
    • 4.7.4 Clock Output Disable Bit (COD) - Bit 19

      58
    • 4.7.5 PLL Pre-Divider Factor (PD0-PD3) - Bits 20-23

      58
  • 4.8 Device Identification (ID) Register

    58
  • 4.9 JTAG Identification (ID) Register

    58
  • 4.10 JTAG Boundary Scan Register (BSR)

    59
• 5 General Purpose Input/Output Port (GPIO)

  61
  • 5.1 Introduction

    61
  • 5.2 GPIO Programming Model

    61
    • 5.2.1 Port B Control Register (PCRB)

      62
      • 5.2.1.1 PCRB Control Bits (PC[3:0]) - Bits 3-0

        62
      • 5.2.1.2 PCRB Reserved Bits - Bits 23-4

        62
      • 5.2.1.3 PRRB Direction Bits (PDC[3:0]) - Bits 3-0

        63
      • 5.2.1.4 PRRB Reserved Bits - Bits 23-4

        63
    • 5.2.2 Port B GPIO Data Register (PDRB)

      63
      • 5.2.2.1 PDRB Data Bits (PD[3:0]) - Bits 3-0

        63
      • 5.2.2.2 PDRB Reserved Bits - Bits 23-4

        63
• 6 Enhanced Serial AUDIO Interface (ESAI)

  65
  • 6.1 Introduction

    65
  • 6.2 ESAI Data and Control Pins

    67
    • 6.2.1 Serial Transmit 0 Data Pin (SDO0)

      67
    • 6.2.2 Serial Transmit 1 Data Pin (SDO1)

      67
    • 6.2.3 Serial Transmit 2/Receive 3 Data Pin (SDO2/SDI3)

      67
    • 6.2.4 Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2)

      68
    • 6.2.5 Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1)

      68
    • 6.2.6 Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0)

      68
    • 6.2.7 Receiver Serial Clock (SCKR)

      68
    • 6.2.8 Transmitter Serial Clock (SCKT)

      69
    • 6.2.9 Frame Sync for Receiver (FSR)

      70
    • 6.2.10 Frame Sync for Transmitter (FST)

      71
    • 6.2.11 High Frequency Clock for Transmitter (HCKT)

      71
    • 6.2.12 High Frequency Clock for Receiver (HCKR)

      71
  • 6.3 ESAI Programming Model

    71
    • 6.3.1 ESAI Transmitter Clock Control Register (TCCR)

      72
      • 6.3.1.1 TCCR Transmit Prescale Modulus Select (TPM7-TPM0) - Bits 0-7

        72
      • 6.3.1.2 TCCR Transmit Prescaler Range (TPSR) - Bit 8

        73
      • 6.3.1.3 TCCR Tx Frame Rate Divider Control (TDC4-TDC0) - Bits 9-13

        74
      • 6.3.1.4 TCCR Tx High Frequency Clock Divider (TFP3-TFP0) - Bits 14-17

        75
      • 6.3.1.5 TCCR Transmit Clock Polarity (TCKP) - Bit 18

        76
      • 6.3.1.6 TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19

        76
      • 6.3.1.7 TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20

        76
      • 6.3.1.8 TCCR Transmit Clock Source Direction (TCKD) - Bit 21

        76
      • 6.3.1.9 TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22

        76
      • 6.3.1.10 TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23

        76
    • 6.3.2 ESAI Transmit Control Register (TCR)

      77
      • 6.3.2.1 TCR ESAI Transmit 0 Enable (TE0) - Bit 0

        77
      • 6.3.2.2 TCR ESAI Transmit 1 Enable (TE1) - Bit 1

        77
      • 6.3.2.3 TCR ESAI Transmit 2 Enable (TE2) - Bit 2

        78
      • 6.3.2.4 TCR ESAI Transmit 3 Enable (TE3) - Bit 3

        78
      • 6.3.2.5 TCR ESAI Transmit 4 Enable (TE4) - Bit 4

        78
      • 6.3.2.6 TCR ESAI Transmit 5 Enable (TE5) - Bit 5

        79
      • 6.3.2.7 TCR Transmit Shift Direction (TSHFD) - Bit 6

        79
      • 6.3.2.8 TCR Transmit Word Alignment Control (TWA) - Bit 7

        79
      • 6.3.2.9 TCR Transmit Network Mode Control (TMOD1-TMOD0) - Bits 8-9

        80
      • 6.3.2.10 TCR Tx Slot and Word Length Select (TSWS4-TSWS0) - Bits 10-14

        82
      • 6.3.2.11 TCR Transmit Frame Sync Length (TFSL) - Bit 15

        83
      • 6.3.2.12 TCR Transmit Frame Sync Relative Timing (TFSR) - Bit 16

        85
      • 6.3.2.13 TCR Transmit Zero Padding Control (PADC) - Bit 17

        85
      • 6.3.2.14 TCR Reserved Bit - Bits 18

        85
      • 6.3.2.15 TCR Transmit Section Personal Reset (TPR) - Bit 19

        85
      • 6.3.2.16 TCR Transmit Exception Interrupt Enable (TEIE) - Bit 20

        85
      • 6.3.2.17 TCR Transmit Even Slot Data Interrupt Enable (TEDIE) - Bit 21

        86
      • 6.3.2.18 TCR Transmit Interrupt Enable (TIE) - Bit 22

        86
      • 6.3.2.19 TCR Transmit Last Slot Interrupt Enable (TLIE) - Bit 23

        86
    • 6.3.3 ESAI Receive Clock Control Register (RCCR)

      86
      • 6.3.3.1 RCCR Receiver Prescale Modulus Select (RPM7-RPM0) - Bits 7-0

        87
      • 6.3.3.2 RCCR Receiver Prescaler Range (RPSR) - Bit 8

        87
      • 6.3.3.3 RCCR Rx Frame Rate Divider Control (RDC4-RDC0) - Bits 9-13

        87
      • 6.3.3.4 RCCR Rx High Frequency Clock Divider (RFP3-RFP0) - Bits 14-17

        88
      • 6.3.3.5 RCCR Receiver Clock Polarity (RCKP) - Bit 18

        88
      • 6.3.3.6 RCCR Receiver Frame Sync Polarity (RFSP) - Bit 19

        88
      • 6.3.3.7 RCCR Receiver High Frequency Clock Polarity (RHCKP) - Bit 20

        88
      • 6.3.3.8 RCCR Receiver Clock Source Direction (RCKD) - Bit 21

        89
      • 6.3.3.9 RCCR Receiver Frame Sync Signal Direction (RFSD) - Bit 22

        89
      • 6.3.3.10 RCCR Receiver High Frequency Clock Direction (RHCKD) - Bit 23

        90
    • 6.3.4 ESAI Receive Control Register (RCR)

      90
      • 6.3.4.1 RCR ESAI Receiver 0 Enable (RE0) - Bit 0

        91
      • 6.3.4.2 RCR ESAI Receiver 1 Enable (RE1) - Bit 1

        91
      • 6.3.4.3 RCR ESAI Receiver 2 Enable (RE2) - Bit 2

        91
      • 6.3.4.4 RCR ESAI Receiver 3 Enable (RE3) - Bit 3

        92
      • 6.3.4.5 RCR Reserved Bits - Bits 4-5, 17-18

        92
      • 6.3.4.6 RCR Receiver Shift Direction (RSHFD) - Bit 6

        92
      • 6.3.4.7 RCR Receiver Word Alignment Control (RWA) - Bit 7

        92
      • 6.3.4.8 RCR Receiver Network Mode Control (RMOD1-RMOD0) - Bits 8-9

        92
      • 6.3.4.9 RCR Receiver Slot and Word Select (RSWS4-RSWS0) - Bits 10-14

        93
      • 6.3.4.10 RCR Receiver Frame Sync Length (RFSL) - Bit 15

        94
      • 6.3.4.11 RCR Receiver Frame Sync Relative Timing (RFSR) - Bit 16

        94
      • 6.3.4.12 RCR Receiver Section Personal Reset (RPR) - Bit 19

        95
      • 6.3.4.13 RCR Receive Exception Interrupt Enable (REIE) - Bit 20

        95
      • 6.3.4.14 RCR Receive Even Slot Data Interrupt Enable (REDIE) - Bit 21

        95
      • 6.3.4.15 RCR Receive Interrupt Enable (RIE) - Bit 22

        95
      • 6.3.4.16 RCR Receive Last Slot Interrupt Enable (RLIE) - Bit 23

        95
    • 6.3.5 ESAI Common Control Register (SAICR)

      96
      • 6.3.5.1 SAICR Serial Output Flag 0 (OF0) - Bit 0

        96
      • 6.3.5.2 SAICR Serial Output Flag 1 (OF1) - Bit 1

        96
      • 6.3.5.3 SAICR Serial Output Flag 2 (OF2) - Bit 2

        96
      • 6.3.5.4 SAICR Reserved Bits - Bits 3-5, 9-23

        96
      • 6.3.5.5 SAICR Synchronous Mode Selection (SYN) - Bit 6

        97
      • 6.3.5.6 SAICR Transmit External Buffer Enable (TEBE) - Bit 7

        97
      • 6.3.5.7 SAICR Alignment Control (ALC) - Bit 8

        97
    • 6.3.6 ESAI Status Register (SAISR)

      98
      • 6.3.6.1 SAISR Serial Input Flag 0 (IF0) - Bit 0

        99
      • 6.3.6.2 SAISR Serial Input Flag 1 (IF1) - Bit 1

        99
      • 6.3.6.3 SAISR Serial Input Flag 2 (IF2) - Bit 2

        99
      • 6.3.6.4 SAISR Reserved Bits - Bits 3-5, 11-12, 18-23

        99
      • 6.3.6.5 SAISR Receive Frame Sync Flag (RFS) - Bit 6

        100
      • 6.3.6.6 SAISR Receiver Overrun Error Flag (ROE) - Bit 7

        100
      • 6.3.6.7 SAISR Receive Data Register Full (RDF) - Bit 8

        100
      • 6.3.6.8 SAISR Receive Even-Data Register Full (REDF) - Bit 9

        100
      • 6.3.6.9 SAISR Receive Odd-Data Register Full (RODF) - Bit 10

        100
      • 6.3.6.10 SAISR Transmit Frame Sync Flag (TFS) - Bit 13

        101
      • 6.3.6.11 SAISR Transmit Underrun Error Flag (TUE) - Bit 14

        101
      • 6.3.6.12 SAISR Transmit Data Register Empty (TDE) - Bit 15

        101
      • 6.3.6.13 SAISR Transmit Even-Data Register Empty (TEDE) - Bit 16

        101
      • 6.3.6.14 SAISR Transmit Odd-Data Register Empty (TODE) - Bit 17

        102
    • 6.3.7 ESAI Receive Shift Registers

      105
    • 6.3.8 ESAI Receive Data Registers (RX3, RX2, RX1, RX0)

      105
    • 6.3.9 ESAI Transmit Shift Registers

      105
    • 6.3.10 ESAI Transmit Data Registers (TX5, TX4, TX3, TX2,TX1,TX0)

      105
    • 6.3.11 ESAI Time Slot Register (TSR)

      105
    • 6.3.12 Transmit Slot Mask Registers (TSMA, TSMB)

      105
    • 6.3.13 Receive Slot Mask Registers (RSMA, RSMB)

      107
  • 6.4 Operating Modes

    108
    • 6.4.1 ESAI After Reset

      108
    • 6.4.2 ESAI Initialization

      108
    • 6.4.3 ESAI Interrupt Requests

      109
    • 6.4.4 Operating Modes - Normal, Network, and On-Demand

      110
      • 6.4.4.1 Normal/Network/On-Demand Mode Selection

        110
      • 6.4.4.2 Synchronous/Asynchronous Operating Modes

        110
      • 6.4.4.3 Frame Sync Selection

        111
      • 6.4.4.4 Shift Direction Selection

        111
    • 6.4.5 Serial I/O Flags

      112
  • 6.5 GPIO - Pins and Registers

    112
    • 6.5.1 Port C Control Register (PCRC)

      112
    • 6.5.2 Port C Direction Register (PRRC)

      113
    • 6.5.3 Port C Data register (PDRC)

      113
  • 6.6 ESAI Initialization Examples

    114
    • 6.6.1 Initializing the ESAI Using Individual Reset

      114
    • 6.6.2 Initializing Just the ESAI Transmitter Section

      115
    • 6.6.3 Initializing Just the ESAI Receiver Section

      115
• 7 Serial Host Interface

  117
  • 7.1 Introduction

    117
  • 7.2 Serial Host Interface Internal Architecture

    118
  • 7.3 SHI Clock Generator

    119
  • 7.4 Serial Host Interface Programming Model

    119
    • 7.4.1 SHI Input/Output Shift Register (IOSR)-Host Side

      121
    • 7.4.2 SHI Host Transmit Data Register (HTX)-DSP Side

      122
    • 7.4.3 SHI Host Receive Data FIFO (HRX)-DSP Side

      122
    • 7.4.4 SHI Slave Address Register (HSAR)-DSP Side

      122
      • 7.4.4.1 HSAR Reserved Bits-Bits 17-0,19

        123
      • 7.4.4.2 HSAR I2C Slave Address (HA[6:3], HA1)-Bits 23-20,18

        123
    • 7.4.5 SHI Clock Control Register (HCKR)-DSP Side

      123
      • 7.4.5.1 Clock Phase and Polarity (CPHA and CPOL)-Bits 1-0

        123
      • 7.4.5.2 HCKR Prescaler Rate Select (HRS)-Bit 2

        125
      • 7.4.5.3 HCKR Divider Modulus Select (HDM[7:0])-Bits 10-3

        125
      • 7.4.5.4 HCKR Reserved Bits-Bits 23-14, 11

        125
      • 7.4.5.5 HCKR Filter Mode (HFM[1:0]) - Bits 13-12

        125
    • 7.4.6 SHI Control/Status Register (HCSR)-DSP Side

      126
      • 7.4.6.1 HCSR Host Enable (HEN)-Bit 0

        126
        • 7.4.6.1.1 SHI Individual Reset

          127
      • 7.4.6.2 HCSR I2C/SPI Selection (HI2C)-Bit 1

        127
      • 7.4.6.3 HCSR Serial Host Interface Mode (HM[1:0])-Bits 3-2

        127
      • 7.4.6.4 HCSR I2C Clock Freeze (HCKFR) - Bit 4

        127
      • 7.4.6.5 HCSR Reserved Bits-Bits 23, 18 and 16

        128
      • 7.4.6.6 HCSR FIFO-Enable Control (HFIFO)-Bit 5

        128
      • 7.4.6.7 HCSR Master Mode (HMST)-Bit 6

        128
      • 7.4.6.8 HCSR Host-Request Enable (HRQE[1:0])-Bits 8-7

        128
      • 7.4.6.9 HCSR Idle (HIDLE)-Bit 9

        129
      • 7.4.6.10 HCSR Bus-Error Interrupt Enable (HBIE)-Bit 10

        129
      • 7.4.6.11 HCSR Transmit-Interrupt Enable (HTIE)-Bit 11

        130
      • 7.4.6.12 HCSR Receive Interrupt Enable (HRIE[1:0])-Bits 13-12

        130
      • 7.4.6.13 HCSR Host Transmit Underrun Error (HTUE)-Bit 14

        131
      • 7.4.6.14 HCSR Host Transmit Data Empty (HTDE)-Bit 15

        131
      • 7.4.6.15 Host Receive FIFO Not Empty (HRNE)-Bit 17

        131
      • 7.4.6.16 Host Receive FIFO Full (HRFF)-Bit 19

        132
      • 7.4.6.17 Host Receive Overrun Error (HROE)-Bit 20

        132
      • 7.4.6.18 Host Bus Error (HBER)-Bit 21

        132
      • 7.4.6.19 HCSR Host Busy (HBUSY)-Bit 22

        132
  • 7.5 SPI Bus Characteristics

    132
  • 7.6 I2C Bus Characteristics

    133
    • 7.6.1 Overview

      133
    • 7.6.2 I2C Data Transfer Formats

      135
  • 7.7 SHI Programming Considerations

    136
    • 7.7.1 SPI Slave Mode

      136
    • 7.7.2 SPI Master Mode

      137
    • 7.7.3 I2C Slave Mode

      137
      • 7.7.3.1 Receive Data in I2C Slave Mode

        138
      • 7.7.3.2 Transmit Data In I2C Slave Mode

        139
    • 7.7.4 I2C Master Mode

      139
      • 7.7.4.1 Receive Data in I2C Master Mode

        140
      • 7.7.4.2 Transmit Data In I2C Master Mode

        141
    • 7.7.5 SHI Operation During DSP Stop

      141
• Appendix A Bootstrap ROM

  143
  • A.1 DSP56364 Bootstrap Program

    143
• Appendix B BDSL File

  151
  • B.1 BSDL FILE

    151
• Appendix C Programmer’s Reference

  157
  • C.1 Introduction

    157
    • C.1.1 Peripheral Addresses

      157
    • C.1.2 Interrupt Addresses

      157
    • C.1.3 Interrupt Priorities

      157
  • C.2 Programming Sheets

    164
• Index

  181