Datenbogen (MCIMX51LCD)Inhaltsverzeichnisi.MX51 Applications Processors for Consumer and Industrial Products11 Introduction11.1 Ordering Information31.2 Block Diagram42 Features52.1 Special Signal Considerations123 IOMUX Configuration for Boot Media143.1 NAND153.2 SD/MMC IOMUX Pin Configuration153.3 I2C IOMUX Pin Configuration153.4 eCSPI/CSPI IOMUX Pin Configuration163.5 Wireless External Interface Module (WEIM)163.6 UART IOMUX Pin Configuration163.7 USB-OTG IOMUX Pin Configuration164 Electrical Characteristics174.1 Chip-Level Conditions174.1.1 Supply Current214.1.2 USB PHY Current Consumption234.2 Supply Power-Up/Power-Down Requirements and Restrictions234.2.1 Power-Up Sequence244.3 I/O DC Parameters244.3.1 GPIO/HSGPIO DC Parameters254.3.2 DDR2 I/O DC Parameters264.3.3 Low Voltage I/O (LVIO) DC Parameters264.3.4 Ultra-High Voltage I/O (UHVIO) DC Parameters274.3.5 I2C I/O DC Parameters294.3.6 USBOTG Electrical DC Parameters294.3.7 USB Port Electrical DC Characteristics304.4 Output Buffer Impedance Characteristics314.4.1 LVIO I/O Output Buffer Impedance314.4.2 DDR2 Output Buffer Impedance324.4.3 UHVIO Output Buffer Impedance334.5 I/O AC Parameters354.5.1 Slow I/O AC Parameters354.5.2 Fast I/O AC Parameters364.5.3 I2C AC Parameters364.5.4 AC Electrical Characteristics for DDR2404.6 Module Timing474.6.1 Reset Timings Parameters474.6.2 WDOG Reset Timing Parameters484.6.3 AUDMUX Timing Parameters484.6.4 Clock Amplifier Parameters (CKIH1, CKIH2)484.6.5 DPLL Electrical Parameters494.6.6 NAND Flash Controller (NFC) Parameters494.6.7 External Interface Module (WEIM)544.6.7.1 WEIM Signal Cross Reference544.6.7.2 WEIM Internal Module Multiplexing554.6.7.3 General WEIM Timing-Synchronous Mode564.6.7.4 Examples of WEIM Synchronous Accesses584.6.7.5 General WEIM Timing-Asynchronous Mode604.6.8 SDRAM Controller Timing Parameters664.6.8.1 Mobile DDR SDRAM Timing Parameters664.6.9 DDR2 SDRAM Specific Parameters694.7 External Peripheral Interfaces744.7.1 CSPI Timing Parameters744.7.1.1 CSPI Master Mode Timing744.7.1.2 CSPI Slave Mode Timing754.7.2 eCSPI Timing Parameters764.7.2.1 eCSPI Master Mode Timing764.7.2.2 eCSPI Slave Mode Timing774.7.3 eSDHCv2 Timing Parameters784.7.4 FEC AC Timing Parameters794.7.4.1 MII Receive Signal Timing794.7.4.2 MII Transmit Signal Timing804.7.4.3 MII Async Inputs Signal Timing (FEC_CRS and FEC_COL)814.7.4.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)814.7.5 Frequency Pre-Multiplier (FPM) Electrical Parameters (CKIL)824.7.6 High-Speed I2C (HS-I2C) Timing Parameters824.7.6.1 Standard and Fast Mode Timing Parameters834.7.6.2 High-Speed Mode Timing Parameters844.7.7 I2C Module Timing Parameters854.7.8 Image Processing Unit (IPU) Module Parameters864.7.8.1 Sensor Interface Timings864.7.8.2 Electrical Characteristics874.7.8.3 IPU Display Interface Signal Mapping884.7.8.4 IPU Display Interface Timing914.7.8.5 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels914.7.8.6 Interface to a TV Encoder974.7.8.7 Asynchronous Interfaces1004.7.8.8 Standard Serial Interfaces1094.7.9 1-Wire Timing Parameters1154.7.10 Pulse Width Modulator (PWM) Timing Parameters1164.7.11 P-ATA Timing Parameters1174.7.11.1 PIO Mode Read Timing1204.7.11.2 Ultra DMA (UDMA) Input Timing1234.7.11.3 UDMA Output Timing1254.7.12 SIM (Subscriber Identification Module) Timing1274.7.12.1 Reset Sequence1284.7.12.2 Power Down Sequence1294.7.13 SCAN JTAG Controller (SJC) Timing Parameters1314.7.14 SPDIF Timing Parameters1334.7.15 SSI Timing Parameters1334.7.15.1 SSI Transmitter Timing with Internal Clock1344.7.15.2 SSI Receiver Timing with Internal Clock1364.7.15.3 SSI Transmitter Timing with External Clock1384.7.15.4 SSI Receiver Timing with External Clock1404.7.16 UART1414.7.16.1 UART Electrical1414.7.17 USBOH3 Parameters1444.7.17.1 USB Serial Interface1444.7.18 USB Parallel Interface Timing1514.7.19 USB PHY Parameters1524.7.19.1 USB PHY AC Parameters1524.7.19.2 USB PHY Additional Electrical Parameters1524.7.19.3 USB PHY System Clocking (SYSCLK)1524.7.19.4 USB PHY Voltage Thresholds1535 Package Information and Contact Assignments1535.1 13 x 13 mm Package Information1535.1.1 BGA-Case 2058 13 x 13 mm, 0.5 mm Pitch1545.1.1.1 13 x 13 mm Package Drawing Notes1545.1.2 13 x 13 mm, 0.5 Pitch Ball Assignment Lists1555.1.2.1 13 x 13 mm Ball Contact Assignments1555.1.2.2 13 x 13 mm Signal Assignments, Power Rails, and I/O1575.1.2.3 13 x 13 mm No Connect Assignments1695.1.3 13 x 13 mm Ball Map1735.2 19 x 19 mm Package Information1735.2.1 BGA-Case 2017, 19 x 19 mm, 0.8 mm Pitch1745.2.1.1 19 x 19 mm Package Drawing Notes1755.2.2 19 x 19 mm Signal Assignments, Power Rails, and I/O1755.2.2.1 19 x 19 mm Ground, Power, Sense, and Reference Contact Assignments1755.2.2.2 19 x 19 mm, Signal Assignments, Power Rails, and I/O1775.2.2.3 Fuse Override Considerations1895.2.3 19 x 19 Ball Map1905.3 13 ¥ 13 mm, 0.5 Pitch Ball Map1915.4 19 x 19 mm, 0.8 Pitch Ball Map1956 Revision History199Größe: 4,05 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