Benutzerhandbuch für Freescale Semiconductor StarterTRAK USB for Automotive Safety Applications TRK-USB-MPC5643L

Inhaltsverzeichnis

• 1 Introduction

  3
  • 1.1 Document overview

    3
  • 1.2 Description

    3
  • 1.3 Device comparison

    3
  • 1.4 Block diagram

    5
  • 1.5 Feature details

    7
    • 1.5.1 High-performance e200z4d core

      7
    • 1.5.2 Crossbar switch (XBAR)

      8
    • 1.5.3 Memory Protection Unit (MPU)

      8
    • 1.5.4 Enhanced Direct Memory Access (eDMA)

      8
    • 1.5.5 On-chip flash memory with ECC

      9
    • 1.5.6 On-chip SRAM with ECC

      9
    • 1.5.7 Platform flash memory controller

      9
    • 1.5.8 Platform Static RAM Controller (SRAMC)

      10
    • 1.5.9 Memory subsystem access time

      10
    • 1.5.10 Error Correction Status Module (ECSM)

      11
    • 1.5.11 Peripheral bridge (PBRIDGE)

      11
    • 1.5.12 Interrupt Controller (INTC)

      11
    • 1.5.13 System clocks and clock generation

      12
    • 1.5.14 Frequency-Modulated Phase-Locked Loop (FMPLL)

      12
    • 1.5.15 Main oscillator

      13
    • 1.5.16 Internal Reference Clock (RC) oscillator

      13
    • 1.5.17 Clock, reset, power, mode and test control modules (MC_CGM, MC_RGM, MC_PCU, and MC_ME)

      13
    • 1.5.18 Periodic Interrupt Timer Module (PIT)

      13
    • 1.5.19 System Timer Module (STM)

      13
    • 1.5.20 Software Watchdog Timer (SWT)

      14
    • 1.5.21 Fault Collection and Control Unit (FCCU)

      14
    • 1.5.22 System Integration Unit Lite (SIUL)

      14
    • 1.5.23 Non-Maskable Interrupt (NMI)

      14
    • 1.5.24 Boot Assist Module (BAM)

      14
    • 1.5.25 System Status and Configuration Module (SSCM)

      15
    • 1.5.26 FlexCAN

      15
    • 1.5.27 FlexRay

      16
    • 1.5.28 Serial communication interface module (LINFlexD)

      16
    • 1.5.29 Deserial Serial Peripheral Interface (DSPI)

      17
    • 1.5.30 FlexPWM

      17
    • 1.5.31 eTimer module

      18
    • 1.5.32 Sine Wave Generator (SWG)

      19
    • 1.5.33 Analog-to-Digital Converter module (ADC)

      19
    • 1.5.34 Cross Triggering Unit (CTU)

      19
    • 1.5.35 Cyclic Redundancy Checker (CRC) Unit

      20
    • 1.5.36 Redundancy Control and Checker Unit (RCCU)

      20
    • 1.5.37 Junction temperature sensor

      20
    • 1.5.38 Nexus Port Controller (NPC)

      20
    • 1.5.39 IEEE 1149.1 JTAG Controller (JTAGC)

      21
    • 1.5.40 Voltage regulator / Power Management Unit (PMU)

      22
    • 1.5.41 Built-In Self-Test (BIST) capability

      22
• 2 Package pinouts and signal descriptions

  23
  • 2.1 Package pinouts

    23
  • 2.2 Supply pins

    52
  • 2.3 System pins

    54
  • 2.4 Pin muxing

    55
• 3 Electrical characteristics

  76
  • 3.1 Introduction

    76
  • 3.2 Absolute maximum ratings

    76
  • 3.3 Recommended operating conditions

    77
  • 3.4 Thermal characteristics

    78
    • 3.4.1 General notes for specifications at maximum junction temperature

      80
      • 3.4.1.1 References

        80
  • 3.5 Electromagnetic Interference (EMI) characteristics

    81
  • 3.6 Electrostatic discharge (ESD) characteristics

    82
  • 3.7 Static latch-up (LU)

    83
  • 3.8 Voltage regulator electrical characteristics

    83
  • 3.9 DC electrical characteristics

    86
  • 3.10 Supply current characteristics

    87
  • 3.11 Temperature sensor electrical characteristics

    90
  • 3.12 Main oscillator electrical characteristics

    90
  • 3.13 FMPLL electrical characteristics

    92
  • 3.14 16 MHz RC oscillator electrical characteristics

    94
  • 3.15 ADC electrical characteristics

    94
    • 3.15.1 Input Impedance and ADC Accuracy

      94
  • 3.16 Flash memory electrical characteristics

    99
  • 3.17 SWG electrical characteristics

    100
  • 3.18 AC specifications

    101
    • 3.18.1 Pad AC specifications

      101
  • 3.19 Reset sequence

    102
    • 3.19.1 Reset sequence duration

      102
    • 3.19.2 Reset sequence description

      102
    • 3.19.3 Reset sequence trigger mapping

      105
    • 3.19.4 Reset sequence - start condition

      106
      • 3.19.4.1 Destructive reset

        106
      • 3.19.4.2 External reset via RESET

        106
    • 3.19.5 External watchdog window

      107
  • 3.20 AC timing characteristics

    107
    • 3.20.1 RESET pin characteristics

      108
    • 3.20.2 WKUP/NMI timing

      109
    • 3.20.3 IEEE 1149.1 JTAG interface timing

      109
    • 3.20.4 Nexus timing

      111
    • 3.20.5 External interrupt timing (IRQ pin)

      114
    • 3.20.6 DSPI timing

      115
• 4 Package characteristics

  120
  • 4.1 Package mechanical data

    120
• 5 Ordering information

  125
• 6 Document revision history

  126