Benutzerhandbuch für Fujitsu MPB3052AT

Inhaltsverzeichnis

• Front title

  1
• PREFACE

  4
• CONTENTS

  8
• FIGURES

  12
• TABLES

  14
• CHAPTER 1 DEVICE OVERVIEW

  16
  • 1.1 Features

    16
    • 1.1.1 Functions and performance

      16
    • 1.1.2 Adaptability

      17
    • 1.1.3 Interface

      17
  • 1.2 Device Specifications

    19
    • 1.2.1 Specifications summary

      19
    • 1.2.2 Model and product number

      20
  • 1.3 Power Requirements

    20
  • 1.4 Environmental Specifications

    23
  • 1.5 Acoustic Noise

    23
  • 1.6 Shock and Vibration

    24
  • 1.7 Reliability

    24
  • 1.8 Error Rate

    25
  • 1.9 Media Defects

    25
• CHAPTER 2 DEVICE CONFIGURATION

  26
  • 2.1 Device Configuration

    26
  • 2.2 System Configuration

    29
    • 2.2.1 ATA interface

      29
    • 2.2.2 1 drive connection

      29
    • 2.2.3 2 drives connection

      30
• CHAPTER 3 INSTALLATION CONDITIONS

  32
  • 3.1 Dimensions

    32
  • 3.2 Mounting

    34
  • 3.3 Cable Connections

    38
    • 3.3.1 Device connector

      38
    • 3.3.2 Cable connector specifications

      39
    • 3.3.3 Device connection

      39
    • 3.3.4 Power supply connector (CN1)

      40
  • 3.4 Jumper Settings

    40
    • 3.4.1 Location of setting jumpers

      40
    • 3.4.2 Factory default setting

      41
    • 3.4.3 Jumper configuration

      41
• CHAPTER 4 THEORY OF DEVICE OPERATION

  44
  • 4.1 Outline

    44
  • 4.2 Subassemblies

    44
    • 4.2.1 Disk

      44
    • 4.2.2 Head

      45
    • 4.2.3 Spindle

      46
    • 4.2.4 Actuator

      46
    • 4.2.5 Air filter

      46
  • 4.3 Circuit Configuration

    47
  • 4.4 Power-on Sequence

    49
  • 4.5 Self-calibration

    51
    • 4.5.1 Self-calibration contents

      51
    • 4.5.2 Execution timing of self-calibration

      52
    • 4.5.3 Command processing during self-calibration

      52
  • 4.6 Read/write Circuit

    53
    • 4.6.1 Read/write preamplifier (PreAMP)

      53
    • 4.6.2 Write circuit

      53
    • 4.6.3 Read circuit

      55
    • 4.6.4 Time base generator circuit

      57
  • 4.7 Servo Control

    58
    • 4.7.1 Servo control circuit

      59
    • 4.7.2 Data-surface servo format

      62
    • 4.7.3 Servo frame format

      62
    • 4.7.4 Actuator motor control

      63
    • 4.7.5 Spindle motor control

      64
• CHAPTER 5 INTERFACE

  66
  • 5.1 Physical Interface

    67
    • 5.1.1 Interface signals

      67
    • 5.1.2 Signal assignment on the connector

      68
  • 5.2 Logical Interface

    71
    • 5.2.1 I/O registers

      71
    • 5.2.2 Command block registers

      73
    • 5.2.3 Control block registers

      78
  • 5.3 Host Commands

    78
    • 5.3.1 Command code and parameters

      79
    • 5.3.2 Command descriptions

      81
    • 5.3.3 Error posting

      120
  • 5.4 Command Protocol

    121
    • 5.4.1 Data transferring commands from device to host

      121
    • 5.4.2 Data transferring commands from host to device

      123
    • 5.4.3 Commands without data transfer

      125
    • 5.4.4 Other commands

      126
    • 5.4.5 DMA data transfer commands

      126
  • 5.5 Ultra DMA feature set

    128
    • 5.5.1 Overview

      128
    • 5.5.2 Phases of operation

      129
    • 5.5.3 Ultra DMA data in commands

      129
      • 5.5.3.1 Initiating an Ultra DMA data in burst

        129
      • 5.5.3.2 The data in transfer

        130
      • 5.5.3.3 Pausing an Ultra DMA data in burst

        130
      • 5.5.3.4 Terminating an Ultra DMA data in burst

        131
    • 5.5.4 Ultra DMA data out commands

      133
      • 5.5.4.1 Initiating an Ultra DMA data out burst

        133
      • 5.5.4.2 The data out transfer

        134
      • 5.5.4.3 Pausing an Ultra DMA data out burst

        134
      • 5.5.4.4 Terminating an Ultra DMA data out burst

        135
    • 5.5.5 Ultra DMA CRC rules

      137
    • 5.5.6 Series termination required for Ultra DMA

      138
  • 5.6 Timing

    139
    • 5.6.1 PIO data transfer

      139
    • 5.6.2 Single word DMA data transfer

      141
    • 5.6.3 Multiword data transfer

      142
    • 5.6.4 Ultra DMA data transfer

      143
      • 5.6.4.1 Initiating an Ultra DMA data in burst

        143
      • 5.6.4.2 Ultra DMA data burst timing requirements

        144
      • 5.6.4.3 Sustained Ultra DMA data in burst

        146
      • 5.6.4.4 Host pausing an Ultra DMA data in burst

        147
      • 5.6.4.5 Device terminating an Ultra DMA data in burst

        148
      • 5.6.4.6 Host terminating an Ultra DMA data in burst

        149
      • 5.6.4.7 Initiating an Ultra DMA data out burst

        150
      • 5.6.4.8 Sustained Ultra DMA data out burst

        151
      • 5.6.4.9 Device pausing an Ultra DMA data out burst

        152
      • 5.6.4.10 Host terminating an Ultra DMA data out burst

        153
      • 5.6.4.11 Device terminating an Ultra DMA data in burst

        154
    • 5.6.5 Power-on and reset

      155
• CHAPTER 6 OPERATIONS

  156
  • 6.1 Device Response to the Reset

    156
    • 6.1.1 Response to power-on

      157
    • 6.1.2 Response to hardware reset

      158
    • 6.1.3 Response to software reset

      159
    • 6.1.4 Response to diagnostic command

      160
  • 6.2 Address Translation

    161
    • 6.2.1 Default parameters

      161
    • 6.2.2 Logical address

      162
  • 6.3 Power Save

    163
    • 6.3.1 Power save mode

      163
    • 6.3.2 Power commands

      165
  • 6.4 Defect Management

    165
    • 6.4.1 Spare area

      166
    • 6.4.2 Alternating defective sectors

      166
  • 6.5 Read-Ahead Cache

    168
    • 6.5.1 Data buffer configuration

      168
    • 6.5.2 Caching operation

      169
    • 6.5.3 Usage of read segment

      170
  • 6.6 Write Cache

    177