Benutzerhandbuch für Hitachi H*/3694F-ZTAT

Inhaltsverzeichnis

• Cover

  1
• Cautions

  3
• Preface

  5
• Contents

  7
• Figures of Contents

  15
• Tables of Contents

  21
• Section 1 Overview

  25
  • 1.1 Overview

    25
  • 1.2 Internal Block Diagram

    26
  • 1.3 Pin Arrangement

    27
  • 1.4 Pin Functions

    29
• Section 2 CPU

  31
  • 2.1 Address Space and Memory Map

    32
  • 2.2 Register Configuration

    34
    • 2.2.1 General Registers

      35
    • 2.2.2 Program Counter (PC)

      36
    • 2.2.3 Condition-Code Register (CCR)

      36
  • 2.3 Data Formats

    38
    • 2.3.1 General Register Data Formats

      38
    • 2.3.2 Memory Data Formats

      40
  • 2.4 Instruction Set

    41
    • 2.4.1 Table of Instructions Classified by Function

      41
    • 2.4.2 Basic Instruction Formats

      50
  • 2.5 Addressing Modesand Effective Address Calculation

    52
    • 2.5.1 Addressing Modes

      52
    • 2.5.2 Effective Address Calculation

      54
  • 2.6 Basic Bus Cycle

    57
    • 2.6.1 Access to On-Chip Memory (RAM, ROM)

      57
    • 2.6.2 On-Chip Peripheral Modules

      58
  • 2.7 CPU States

    59
  • 2.8 Usage Notes

    60
    • 2.8.1 Notes on Data Access to Empty Areas

      60
    • 2.8.2 EEPMOV Instruction

      60
    • 2.8.3 Bit Manipulation Instruction

      60
• Section 3 Exception Handling

  67
  • 3.1 Exception Sources and Vector Address

    67
  • 3.2 Register Descriptions

    69
    • 3.2.1 Interrupt Edge Select Register 1(IEGR1)

      69
    • 3.2.2 Interrupt Edge Select Register 2(IEGR2)

      70
    • 3.2.3 Interrupt Enable Register 1(IENR1)

      71
    • 3.2.4 Interrupt Flag Register 1(IRR1)

      72
    • 3.2.5 Wakeup Interrupt Flag Register(IWPR)

      73
  • 3.3 Reset

    74
  • 3.4 Interrupt Exception Handling

    74
    • 3.4.1 External Interrupts

      74
    • 3.4.2 Internal Interrupts

      75
    • 3.4.3 Interrupt Handling Sequence

      76
    • 3.4.4 Interrupt Response Time

      77
  • 3.5 Usage Notes

    79
    • 3.5.1 Interrupts after Reset

      79
    • 3.5.2 Notes on Stack Area Use

      79
    • 3.5.3 Notes on Rewriting Port Mode Registers

      79
• Section 4 Address Break

  81
  • 4.1 Register Descriptions

    81
    • 4.1.1 Address Break Control Register(ABRKCR)

      82
    • 4.1.2 Address Break Status Register(ABRKSR)

      83
    • 4.1.3 Break Address Registers (BARH, BARL)

      83
    • 4.1.4 Break Data Registers (BDRH, BDRL)

      84
  • 4.2 Operation

    84
• Section 5 Clock Pulse Generators

  87
  • 5.1 System Clock Generator

    87
    • 5.1.1 Connecting a Crystal Oscillator

      88
    • 5.1.2 Connecting a Ceramic Oscillator

      89
    • 5.1.3 External Clock Input Method

      89
  • 5.2 Subclock Generator

    89
    • 5.2.1 Connecting a 32.768-kHz Crystal Oscillator

      90
    • 5.2.2 Pin Connection when Not Using Subclock

      90
  • 5.3 Prescalers

    91
    • 5.3.1 Prescaler S

      91
    • 5.3.2 Prescaler W

      91
  • 5.4 Usage Notes

    91
    • 5.4.1 Note on Oscillators

      91
    • 5.4.2 Notes on Board Design

      92
• Section 6 Power-down Modes

  93
  • 6.1 Register Descriptions

    93
    • 6.1.1 System Control Register 1(SYSCR1)

      94
    • 6.1.2 System Control Register 2(SYSCR2)

      96
    • 6.1.3 Module Standby Control Register 1(MSTCR1)

      96
  • 6.2 Mode Transitions and States of the LSI

    97
    • 6.2.1 Sleep Mode

      100
    • 6.2.2 Standby Mode

      101
    • 6.2.3 Subsleep Mode

      101
    • 6.2.4 Subactive Mode

      102
  • 6.3 Operating Frequency in the Active Mode

    102
  • 6.4 Direct Transition

    102
    • 6.4.1 Direct Transition from the Active Mode to the Subactive Mode

      102
    • 6.4.2 Direct Transition from the Subactive Mode to the Active Mode

      103
  • 6.5 Module Standby Function

    103
• Section 7 ROM

  105
  • 7.1 Block Configuration

    105
  • 7.2 Register Descriptions

    106
    • 7.2.1 Flash Memory Control Register 1 (FLMCR1)

      107
    • 7.2.2 Flash Memory Control Register 2 (FLMCR2)

      108
    • 7.2.3 Erase Block Register 1 (EBR1)

      108
    • 7.2.4 Flash Memory Power Control Register (FLPWCR)

      109
    • 7.2.5 Flash Memory Enable Register (FENR)

      109
  • 7.3 On-Board Programming Modes

    110
    • 7.3.1 Boot Mode

      110
    • 7.3.2 Programming/Erasing in User Program Mode

      113
  • 7.4 Flash Memory Programming/Erasing

    114
    • 7.4.1 Program/Program-Verify

      114
    • 7.4.2 Erase/Erase-Verify

      116
    • 7.4.3 Interrupt Handling when Programming/Erasing Flash Memory

      117
  • 7.5 Program/Erase Protection

    119
    • 7.5.1 Hardware Protection

      119
    • 7.5.2 Software Protection

      119
    • 7.5.3 Error Protection

      119
  • 7.6 Programmer Mode

    120
    • 7.6.1 Socket Adapter

      120
    • 7.6.2 Programmer Mode Commands

      120
    • 7.6.3 Memory Read Mode

      122
    • 7.6.4 Auto-Program Mode

      124
    • 7.6.5 Auto-Erase Mode

      126
    • 7.6.6 Status Read Mode

      128
    • 7.6.7 Status Polling

      129
    • 7.6.8 Programmer Mode Transition Time

      130
    • 7.6.9 Notes on Memory Programming

      130
  • 7.7 Power-Down States for Flash Memory

    131
• Section 8 RAM

  133
• Section 9 I/O Ports

  135
  • 9.1 Port 1

    135
    • 9.1.1 Port Mode Register 1(PMR1)

      136
    • 9.1.2 Port Control Register 1(PCR1)

      137
    • 9.1.3 Port Data Register 1(PDR1)

      137
    • 9.1.4 Port Pull-Up Control Register 1(PUCR1)

      138
    • 9.1.5 Pin Functions

      138
  • 9.2 Port 2

    140
    • 9.2.1 Port Control Register 2(PCR2)

      140
    • 9.2.2 Port Data Register 2(PDR2)

      141
    • 9.2.3 Pin Functions

      141
  • 9.3 Port 5

    142
    • 9.3.1 Port Mode Register 5(PMR5)

      143
    • 9.3.2 Port Control Register 5(PCR5)

      144
    • 9.3.3 Port Data Register 5(PDR5)

      144
    • 9.3.4 Port Pull-up Control Register 5(PUCR5)

      145
    • 9.3.5 Pin Functions

      145
  • 9.4 Port 7

    147
    • 9.4.1 Port Control Register 7(PCR7)

      148
    • 9.4.2 Port Data Register 7(PDR7)

      148
    • 9.4.3 Pin Functions

      149
  • 9.5 Port 8

    150
    • 9.5.1 Port Control Register 8(PCR8)

      150
    • 9.5.2 Port Data Register 8(PDR8)

      151
    • 9.5.3 Pin Functions

      151
  • 9.6 Port B

    153
    • 9.6.1 Port Data Register B(PDRB)

      154
• Section 10 Timer A

  155
  • 10.1 Features

    155
  • 10.2 Input/Output Pins

    156
  • 10.3 Register Descriptions

    156
    • 10.3.1 Timer Mode Register A(TMA)

      157
    • 10.3.2 Timer Counter A (TCA)

      158
  • 10.4 Operation

    158
    • 10.4.1 Interval Timer Operation

      158
    • 10.4.2 Clock Time Base Operation

      158
    • 10.4.3 Clock Output

      158
  • 10.5 Usage Note

    159
• Section 11 Timer V

  161
  • 11.1 Features

    161
  • 11.2 Input/Output Pins

    162
  • 11.3 Register Descriptions

    163
    • 11.3.1 Timer Counter V (TCNTV)

      163
    • 11.3.2 Time Constant Registers A and B (TCORA, TCORB)

      163
    • 11.3.3 Timer Control Register V0(TCRV0)

      164
    • 11.3.4 Timer Control/Status Register V(TCSRV)

      166
    • 11.3.5 Timer Control Register V1(TCRV1)

      167
  • 11.4 Operation

    168
    • 11.4.1 Timer V operation

      168
  • 11.5 Timer V application examples

    170
    • 11.5.1 Pulse Output with Arbitrary Duty Cycle

      170
    • 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input

      171
  • 11.6 Usage Notes

    172
• Section 12 Timer W

  175
  • 12.1 Features

    175
  • 12.2 Input/Output Pins

    177
  • 12.3 Register Descriptions

    178
    • 12.3.1 Timer Mode Register W(TMRW)

      178
    • 12.3.2 Timer Control Register W(TCRW)

      180
    • 12.3.3 Timer Interrupt Enable Register W(TIERW)

      181
    • 12.3.4 Timer Status Register W(TSRW)

      181
    • 12.3.5 Timer I/O Control Register 0(TIOR0)

      183
    • 12.3.6 Timer I/O Control Register 1(TIOR1)

      184
    • 12.3.7 Timer Counter (TCNT)

      185
    • 12.3.8 General Registers A to D (GRA to GRD)

      185
  • 12.4 Operation

    186
    • 12.4.1 Normal Operation

      186
    • 12.4.2 PWM Operation

      190
  • 12.5 Operation Timing

    194
    • 12.5.1 TCNT Count Timing

      194
    • 12.5.2 Output Compare Timing

      194
    • 12.5.3 Input Capture Timing

      195
    • 12.5.4 Timing of Counter Clearing by Compare Match

      196
    • 12.5.5 Buffer Operation Timing

      196
    • 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match

      197
    • 12.5.7 Timing of IMFA to IMFD Setting at Input Capture

      198
    • 12.5.8 Timing of Status Flag Clearing

      198
  • 12.6 Usage Notes

    199
• Section 13 Watchdog Timer

  201
  • 13.1 Features

    201
  • 13.2 Register Descriptions

    201
    • 13.2.1 Timer Control/Status Register WD(TCSRWD)

      202
    • 13.2.2 Timer Counter WD(TCWD)

      203
    • 13.2.3 Timer Mode Register WD(TMWD)

      203
  • 13.3 Operation

    204
• Section 14 Serial Communication Interface3 (SCI3)

  205
  • 14.1 Features

    205
  • 14.2 Input/Output Pins

    207
  • 14.3 Register Descriptions

    207
    • 14.3.1 Receive Shift Register (RSR)

      208
    • 14.3.2 Receive Data Register (RDR)

      208
    • 14.3.3 Transmit Shift Register (TSR)

      208
    • 14.3.4 Transmit Data Register (TDR)

      208
    • 14.3.5 Serial Mode Register (SMR)

      209
    • 14.3.6 Serial Control Register 3 (SCR3)

      210
    • 14.3.7 Serial Status Register (SSR)

      212
    • 14.3.8 Bit Rate Register (BRR)

      214
  • 14.4 Operation in Asynchronous Mode

    219
    • 14.4.1 Clock

      219
    • 14.4.2 SCI Initialization

      220
    • 14.4.3 Data Transmission

      221
    • 14.4.4 Serial Data Reception

      223
  • 14.5 Operation in Clocked Synchronous Mode

    227
    • 14.5.1 Clock

      227
    • 14.5.2 SCI Initialization

      227
    • 14.5.3 Serial Data Transmission

      228
    • 14.5.4 Serial Data Reception (Clocked Synchronous Mode)

      230
    • 14.5.5 Simultaneous Serial Data Transmission and Reception

      232
  • 14.6 Multiprocessor Communication Function

    234
    • 14.6.1 Multiprocessor Serial Data Transmission

      236
    • 14.6.2 Multiprocessor Serial Data Reception

      237
  • 14.7 Interrupts

    241
  • 14.8 Usage Notes

    242
    • 14.8.1 Break Detection and Processing

      242
    • 14.8.2 Mark State and Break Detection

      242
    • 14.8.3 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)

      242
    • 14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode

      243
• Section 15 I2C Bus Interface 2 (IIC2)

  245
  • 15.1 Features

    245
  • 15.2 Input/Output Pins

    247
  • 15.3 Register Descriptions

    247
    • 15.3.1 I2C Bus Control Register 1 (ICCR1)

      248
    • 15.3.2 I2C Bus Control Register 2 (ICCR2)

      249
    • 15.3.3 I2C Bus Mode Register (ICMR)

      251
    • 15.3.4 I2C Bus Interrupt Enable Register (ICIER)

      252
    • 15.3.5 I2C Bus Status Register (ICSR)

      254
    • 15.3.6 Slave Address Register (SAR)

      256
    • 15.3.7 I2C Bus Transmit Data Register (ICDRT)

      257
    • 15.3.8 I2C Bus Receive Data Register (ICDRR)

      257
    • 15.3.9 I2C Bus Shift Register (ICDRS)

      257
  • 15.4 Operation

    258
    • 15.4.1 I2C Bus Format

      258
    • 15.4.2 Master Transmit Operation

      259
    • 15.4.3 Master Receive Operation

      261
    • 15.4.4 Slave Transmit Operation

      263
    • 15.4.5 Slave Receive Operation

      265
    • 15.4.6 Clocked Synchronous Serial Format

      267
    • 15.4.7 Noise Canceler

      269
    • 15.4.8 Example of Use

      270
  • 15.5 Interrupt Request

    274
  • 15.6 Bit Synchronous Circuit

    275
• Section 16 A/D Converter

  277
  • 16.1 Features

    277
  • 16.2 Input/Output Pins

    279
  • 16.3 Register Description

    280
    • 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD)

      280
    • 16.3.2 A/D Control/Status Register (ADCSR)

      281
    • 16.3.3 A/D Control Register (ADCR)

      282
  • 16.4 Operation

    283
    • 16.4.1 Single Mode

      283
    • 16.4.2 Scan Mode

      283
    • 16.4.3 Input Sampling and A/D Conversion Time

      284
    • 16.4.4 External Trigger Input Timing

      285
  • 16.5 A/D Conversion Accuracy Definitions

    286
  • 16.6 Usage Notes

    287
    • 16.6.1 Permissible Signal Source Impedance

      287
    • 16.6.2 Influences on Absolute Precision

      287
• Section 17 Power-on Reset and Low-Voltage Detection Circuits (Optional)

  289
  • 17.1 Features

    289
  • 17.2 Register Descriptions

    290
    • 17.2.1 Low-Voltage-Detection Control Register (LVDCR)

      290
    • 17.2.2 Low-Voltage-Detection Status Register (LVDSR)

      292
  • 17.3 Operation

    292
    • 17.3.1 Power-on Reset Circuit

      292
    • 17.3.2 Low-Voltage Detection Circuit

      293
• Section 18 Power Supply Circuit

  297
  • 18.1 When Using the Internal Power Supply Step-Down Circuit

    297
  • 18.2 When Not Using the Internal Power Supply Step-Down Circuit

    298
• Section 19 Internal I/O Registers

  299
  • 19.1 Register Addresses

    299
  • 19.2 Register Bits

    303
  • 19.3 Registers States in Each Operating Mode

    306
• Section 20 Electrical Characteristics

  309
  • 20.1 Absolute Maximum Ratings

    309
  • 20.2 Electrical Characteristics (F-ZTAT™ Version)

    309
    • 20.2.1 Power Supply Voltage and Operating Ranges

      309
    • 20.2.2 DC Characteristics

      311
    • 20.2.3 AC Characteristics

      317
    • 20.2.4 A/D Converter Characteristics

      321
    • 20.2.5 Watchdog Timer Characteristics

      322
    • 20.2.6 Flash Memory Characteristics

      323
    • 20.2.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional)

      325
  • 20.3 Electrical Characteristics (Mask ROM Version)

    326
    • 20.3.1 Power Supply Voltage and Operating Ranges

      326
    • 20.3.2 DC Characteristics

      327
    • 20.3.3 AC Characteristics

      333
    • 20.3.4 A/D Converter Characteristics

      337
    • 20.3.5 Watchdog Timer

      338
    • 20.3.6 Power-Supply-Voltage Detection Circuit Characteristics (Optional)

      339
  • 20.4 Operation Timing

    339
  • 20.5 Output Load Circuit

    341
• Appendix A Instruction Set

  343
  • A.1 Instruction List

    343
  • A.2 Operation Code Map

    358
  • A.3 Number of Execution States

    361
  • A.4 Combinations of Instructions and Addressing Modes

    372
• Appendix B I/O Port Block Diagrams

  373
  • B.1 I/O Port Block

    373
  • B.2 Port States in Each Operating State

    389
• Appendix C Product Code Lineup

  390
• Appendix D Package Dimensions

  391
• Index

  393