BenutzerhandbuchInhaltsverzeichnisAbout This Document9Intel 80960Hx Processor9The i960® Processor Family10Key 80960Hx Features102.2.1 Execution Architecture102.2.2 Pipelined, Burst Bus102.2.3 On-Chip Caches and Data RAM112.2.4 Priority Interrupt Controller112.2.5 Guarded Memory Unit112.2.6 Dual Programmable Timers122.2.7 Processor Self Test12Instruction Set Summary13Package Information14Pin Descriptions1580960Hx Mechanical Data203.2.1 80960Hx PGA Pinout203.2.2 80960Hx PQ4 Pinout26Package Thermal Specifications31Heat Sink Adhesives34PowerQuad4 Plastic Package34Stepping Register Information34Sources for Accessories36Electrical Specifications37Absolute Maximum Ratings37Operating Conditions37Recommended Connections38VCC5 Pin Requirements (VDIFF)38VCCPLL Pin Requirements39DC Specifications40AC Specifications424.7.1 AC Test Conditions45AC Timing Waveforms46Bus Waveforms5480960Hx Boundary Scan Chain84Boundary Scan Description Language Example8880960Hx Block Diagram980960Hx 168-Pin PGA Pinout—View from Top (Pins Facing Down)2080960Hx 168-Pin PGA Pinout—View from Bottom (Pins Facing Up)2180960Hx 208-Pin PQ4 Pinout26Measuring 80960Hx PGA Case Temperature3180960Hx Device Identification Register34VCC5 Current-Limiting Resistor38AC Test Load45CLKIN Waveform46Output Delay Waveform46Output Delay Waveform46Output Float Waveform47Input Setup and Hold Waveform47NMI, XINT7:0 Input Setup and Hold Waveform47Hold Acknowledge Timings48Bus Backoff (BOFF) Timings48TCK Waveform49Input Setup and Hold Waveforms for TBSIS1 and TBSIH149Output Delay and Output Float for TBSOV1 and TBSOF150Output Delay and Output Float Waveform for TBSOV2 and TBSOF250Input Setup and Hold Waveform for TBSIS2 and TBSIH250Rise and Fall Time Derating at 85 °C and Minimum VCC51ICC Active (Power Supply) vs. Frequency51ICC Active (Thermal) vs. Frequency52Output Delay or Hold vs. Load Capacitance52Output Delay vs. Temperature53Output Hold Times vs. Temperature53Output Delay vs. VCC53Cold Reset Waveform54Warm Reset Waveform55Entering ONCE Mode56Non-Burst, Non-Pipelined Requests without Wait States57Non-Burst, Non-Pipelined Read Request with Wait States58Non-Burst, Non-Pipelined Write Request with Wait States59Burst, Non-Pipelined Read Request without Wait States, 32-Bit Bus60Burst, Non-Pipelined Read Request with Wait States, 32-Bit Bus61Burst, Non-Pipelined Write Request without Wait States, 32-Bit Bus62Burst, Non-Pipelined Write Request with Wait States, 32-Bit Bus63Burst, Non-Pipelined Read Request with Wait States, 16-Bit Bus64Burst, Non-Pipelined Read Request with Wait States, 8-Bit Bus65Non-Burst, Pipelined Read Request without Wait States, 32-Bit Bus66Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus67Burst, Pipelined Read Request without Wait States, 32-Bit Bus68Burst, Pipelined Read Request with Wait States, 32-Bit Bus69Burst, Pipelined Read Request with Wait States, 8-Bit Bus70Burst, Pipelined Read Request with Wait States, 16-Bit Bus71Using External READY72Terminating a Burst with BTERM73BREQ and BSTALL Operation74BOFF Functional Timing. BOFF occurs during a burst or non-burst data cycle.75HOLD Functional Timing76LOCK Delays HOLDA Timing77FAIL Functional Timing77A Summary of Aligned and Unaligned Transfers for 32-Bit Regions78A Summary of Aligned and Unaligned Transfers for 32-Bit Regions (Continued)79A Summary of Aligned and Unaligned Transfers for 16-Bit Bus8057 A Summary of Aligned and Unaligned Transfers for 8-Bit Bus8158 Idle Bus Operation8259 Bus States8380960Hx Product Description9Fail Codes For BIST (bit 7 = 1)12Remaining Fail Codes (bit 7 = 0)1280960Hx Instruction Set1380960HA/HD/HT Package Types and Speeds14Pin Description Nomenclature1580960Hx Processor Family Pin Descriptions1680960Hx 168-Pin PGA Pinout—Signal Name Order2280960Hx 168-Pin PGA Pinout—Pin Number Order2480960Hx PQ4 Pinout—Signal Name Order2780960Hx PQ4 Pinout—Pin Number Order2980960Hx 168-Pin PGA Package Thermal Characteristics32Maximum TA at Various Airflows in °C (PGA Package Only)3280960Hx 208-Pin PQ4 Package Thermal Characteristics33Maximum TA at Various Airflows in °C (PQ4 Package Only)3380960Hx Device ID Model Types35Device ID Version Numbers for Different Steppings35Fields of 80960Hx Device ID35Absolute Maximum Ratings37Operating Conditions37VDIFF Specification for Dual Power Supply Requirements (3.3 V, 5 V)3980960Hx DC Characteristics4080960Hx AC Characteristics4280960Hx Boundary Scan Test Signal Timings44AC Characteristics Notes4480960Hx Boundary Scan Chain84Größe: 997 KBSeiten: 104Language: EnglishHandbuch öffnen
