BenutzerhandbuchInhaltsverzeichnis8XC196NP, 80C196NU Microcontroller User’s Manual2CONTENTS4CHAPTER 1 GUIDE TO THIS MANUAL201.1 MANUAL CONTENTS201.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY221.3 RELATED DOCUMENTS241.4 ELECTRONIC SUPPORT SYSTEMS271.4.4 World Wide Web301.5 TECHNICAL SUPPORT301.6 PRODUCT LITERATURE30CHAPTER 2 ARCHITECTURAL OVERVIEW342.1 TYPICAL APPLICATIONS342.2 DEVICE FEATURES352.3 BLOCK DIAGRAM352.3.1 CPU Control362.3.2 Register File362.3.3 Register Arithmetic-logic Unit (RALU)372.3.3.1 Code Execution372.3.3.2 Instruction Format382.3.4 Memory Controller382.3.5 Multiply-accumulate (80C196NU Only)392.3.6 Interrupt Service392.4 INTERNAL TIMING402.5 INTERNAL PERIPHERALS442.5.1 I/O Ports442.5.2 Serial I/O (SIO) Port442.5.3 Event Processor Array (EPA) and Timer/Counters442.5.4 Pulse-width Modulator (PWM)452.6 SPECIAL OPERATING MODES452.6.1 Reducing Power Consumption452.6.2 Testing the Printed Circuit Board462.7 DESIGN CONSIDERATIONS FOR 80C196NP TO 80C196NU CONVERSIONS46CHAPTER 3 ADVANCED MATH FEATURES503.1 ENHANCED MULTIPLICATION INSTRUCTIONS3.1 ENHANCED MULTIPLICATION INSTRUCTIONS503.2 OPERATING MODES513.2.1 Saturation Mode513.2.2 Fractional Mode523.3 ACCUMULATOR REGISTER (ACC_0 x)533.4 ACCUMULATOR CONTROL AND STATUS REGISTER (ACC_STAT)54CHAPTER 4 PROGRAMMING CONSIDERATIONS584.1 OVERVIEW OF THE INSTRUCTION SET584.1.1 BIT Operands594.1.2 BYTE Operands594.1.3 SHORT-INTEGER Operands594.1.4 WORD Operands604.1.5 INTEGER Operands604.1.6 DOUBLE-WORD Operands604.1.7 LONG-INTEGER Operands614.1.8 QUAD-WORD Operands614.1.9 Converting Operands614.1.10 Conditional Jumps614.1.11 Floating Point Operations624.1.12 Extended Instructions624.2 ADDRESSING MODES634.2.1 Direct Addressing644.2.2 Immediate Addressing644.2.3 Indirect Addressing644.2.3.1 Extended Indirect Addressing654.2.3.2 Indirect Addressing with Autoincrement654.2.3.3 Extended Indirect Addressing with Autoincrement654.2.3.4 Indirect Addressing with the Stack Pointer664.2.4 Indexed Addressing664.2.4.1 Short-indexed Addressing664.2.4.2 Long-indexed Addressing664.2.4.3 Extended Indexed Addressing674.2.4.4 Zero-indexed Addressing674.2.4.5 Extended Zero-indexed Addressing674.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS684.3.1 Direct Addressing684.3.2 Indexed Addressing684.3.3 Extended Addressing684.4 DESIGN CONSIDERATIONS FOR 1-MBYTE DEVICES684.5 SOFTWARE STANDARDS AND CONVENTIONS684.5.1 Using Registers694.5.2 Addressing 32-bit Operands694.5.3 Addressing 64-bit Operands694.5.4 Linking Subroutines704.6 SOFTWARE PROTECTION FEATURES AND GUIDELINES71CHAPTER 5 MEMORY PARTITIONS745.1 MEMORY MAP OVERVIEW745.2 MEMORY PARTITIONS765.2.1 External Memory785.2.2 Program and Special-purpose Memory785.2.2.1 Program Memory in Page FFH785.2.2.2 Special-purpose Memory795.2.2.3 Reserved Memory Locations805.2.2.4 Interrupt and PTS Vectors805.2.2.5 Chip Configuration Bytes805.2.3 Peripheral Special-function Registers (SFRs)805.2.4 Register File825.2.4.1 General-purpose Register RAM845.2.4.2 Stack Pointer (SP)845.2.4.3 CPU Special-function Registers (SFRs)855.3 WINDOWING865.3.1 Selecting a Window875.3.2 Addressing a Location Through a Window895.3.2.1 32-byte Windowing Example915.3.2.2 64-byte Windowing Example915.3.2.3 128-byte Windowing Example915.3.2.4 Unsupported Locations Windowing Example (8XC196NP Only)925.3.2.5 Using the Linker Locator to Set Up a Window925.3.3 Windowing and Addressing Modes945.4 REMAPPING INTERNAL ROM (83C196NP ONLY)955.5 FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES965.5.1 Fetching Instructions965.5.2 Accessing Data965.5.3 Code Fetches in the 1-Mbyte Mode985.5.4 Code Fetches in the 64-Kbyte Mode985.5.5 Data Fetches in the 1-Mbyte and 64-Kbyte Modes355.6 MEMORY CONFIGURATION EXAMPLES1005.6.1 Example 1: Using the 64-Kbyte Mode1005.6.2 Example 2: A 64-Kbyte System with Additional Data Storage1025.6.3 Example 3: Using 1-Mbyte Mode104CHAPTER 6 STANDARD AND PTS INTERRUPTS1086.1 OVERVIEW OF INTERRUPTS1086.2 INTERRUPT SIGNALS AND REGISTERS1106.3 INTERRUPT SOURCES AND PRIORITIES1116.3.1 Special Interrupts1116.3.1.1 Unimplemented Opcode1126.3.1.2 Software Trap1126.3.1.3 NMI1136.3.2 External Interrupt Pins1136.3.3 Multiplexed Interrupt Sources1136.3.4 End-of-PTS Interrupts1136.4 INTERRUPT LATENCY1146.4.1 Situations that Increase Interrupt Latency1146.4.2 Calculating Latency1156.4.2.1 Standard Interrupt Latency1156.4.2.2 PTS Interrupt Latency1166.5 PROGRAMMING THE INTERRUPTS1176.5.1 Programming Considerations for Multiplexed Interrupts1186.5.2 Modifying Interrupt Priorities1206.5.3 Determining the Source of an Interrupt1226.6 INITIALIZING THE PTS CONTROL BLOCKS1246.6.1 Specifying the PTS Count1256.6.2 Selecting the PTS Mode1266.6.3 Single Transfer Mode1276.6.4 Block Transfer Mode1306.6.5 PWM Modes1336.6.5.1 PWM Toggle Mode Example1346.6.5.2 PWM Remap Mode Example139CHAPTER 7 I/O PORTS1467.1 I/O PORTS OVERVIEW1467.2 BIDIRECTIONAL PORTS 1–41467.2.1 Bidirectional Port Operation1487.2.2 Bidirectional Port Pin Configurations1527.2.3 Bidirectional Port Pin Configuration Example1537.2.4 Bidirectional Port Considerations1547.2.5 Design Considerations for External Interrupt Inputs1567.3 EPORT1567.3.1 EPORT Operation1577.3.1.1 Reset1597.3.1.2 Output Enable1597.3.1.3 Complementary Output Mode1597.3.1.4 Open-drain Output Mode1597.3.1.5 Input Mode1617.3.2 Configuring EPORT Pins1627.3.2.1 Configuring EPORT Pins for Extended-address Functions1627.3.2.2 Configuring EPORT Pins for I/O1627.3.3 EPORT Considerations1637.3.3.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold.1637.3.3.2 EP_REG Settings for Pins Configured as Extended-address Signals1637.3.3.3 EPORT Status During Instruction Execution1637.3.3.4 Design Considerations164CHAPTER 8 SERIAL I/O (SIO) PORT1688.1 SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW1688.2 SERIAL I/O PORT SIGNALS AND REGISTERS1698.3 SERIAL PORT MODES1718.3.1 Synchronous Mode (Mode 0)1718.3.2 Asynchronous Modes (Modes 1, 2, and 3)1728.3.2.1 Mode 11738.3.2.2 Mode 21748.3.2.3 Mode 31748.3.2.4 Mode 2 and 3 Timings1748.3.2.5 Multiprocessor Communications1758.4 PROGRAMMING THE SERIAL PORT1758.4.1 Configuring the Serial Port Pins1758.4.2 Programming the Control Register1758.4.2 Programming the Control Register1758.4.3 Programming the Baud Rate and Clock Source1758.4.4 Enabling the Serial Port Interrupts1808.4.5 Determining Serial Port Status180CHAPTER 9 PULSE-WIDTH MODULATOR1869.1 PWM FUNCTIONAL OVERVIEW1869.2 PWM SIGNALS AND REGISTERS1879.3 PWM OPERATION1889.4 PROGRAMMING THE FREQUENCY AND PERIOD1909.5 PROGRAMMING THE DUTY CYCLE1929.5.1 Sample Calculations1949.5.2 Enabling the PWM Outputs1949.5.3 Generating Analog Outputs194CHAPTER 10 EVENT PROCESSOR ARRAY (EPA)19810.1 EPA FUNCTIONAL OVERVIEW19810.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS19910.3 TIMER/COUNTER FUNCTIONAL OVERVIEW20210.3.1 Cascade Mode (Timer 2 Only)20310.3.2 Quadrature Clocking Mode20310.4 EPA CHANNEL FUNCTIONAL OVERVIEW20510.4.1 Operating in Capture Mode20610.4.1.1 EPA Overruns20810.4.1.2 Preventing EPA Overruns20910.4.2 Operating in Compare Mode20910.4.2.1 Generating a Low-speed PWM Output20910.4.2.2 Generating a Medium-speed PWM Output21010.4.2.3 Generating a High-speed PWM Output21110.4.2.4 Generating the Highest-speed PWM Output21210.5 PROGRAMMING THE EPA AND TIMER/COUNTERS21210.5.1 Configuring the EPA and Timer/Counter Port Pins21210.5.2 Programming the Timers21210.5.3 Programming the Capture/Compare Channels21510.6 ENABLING THE EPA INTERRUPTS21910.7 DETERMINING EVENT STATUS21910.7.1 Using Software to Service the Multiplexed Overrun Interrupts22010.8 PROGRAMMING EXAMPLES FOR EPA CHANNELS22110.8.1 EPA Compare Event Program22110.8.2 EPA Capture Event Program22210.8.3 EPA PWM Output Program223CHAPTER 11 MINIMUM HARDWARE CONSIDERATIONS22811.1 MINIMUM CONNECTIONS22811.1.1 Unused Inputs22911.1.2 I/O Port Pin Connections22911.2 APPLYING AND REMOVING POWER23111.3 NOISE PROTECTION TIPS23111.4 THE ON-CHIP OSCILLATOR CIRCUITRY23211.5 USING AN EXTERNAL CLOCK SOURCE23411.6 RESETTING THE DEVICE23511.6.1 Generating an External Reset23611.6.2 Issuing the Reset (RST) Instruction23811.6.3 Issuing an Illegal IDLPD Key Operand238CHAPTER 12 SPECIAL OPERATING MODES24212.1 SPECIAL OPERATING MODE SIGNALS AND REGISTERS24212.2 REDUCING POWER CONSUMPTION24412.3 IDLE MODE24612.4 STANDBY MODE (80C196NU ONLY)24712.4.1 Enabling and Disabling Standby Mode24712.4.2 Entering Standby Mode24712.4.3 Exiting Standby Mode24812.5 POWERDOWN MODE24812.5.1 Enabling and Disabling Powerdown Mode24812.5.2 Entering Powerdown Mode24812.5.3 Exiting Powerdown Mode24912.5.3.1 Generating a Hardware Reset24912.5.3.2 Asserting an External Interrupt Signal24912.5.3.3 Selecting C125112.6 ONCE MODE25312.7 RESERVED TEST MODES (80C196NU ONLY)253CHAPTER 13 INTERFACING WITH EXTERNAL MEMORY25813.1 INTERNAL AND EXTERNAL ADDRESSES25813.2 EXTERNAL MEMORY INTERFACE SIGNALS25913.3 THE CHIP-SELECT UNIT26213.3.1 Defining Chip-select Address Ranges26413.3.2 Controlling Wait States, Bus Width, and Bus Multiplexing26713.3.3 Chip-select Unit Initial Conditions26813.3.4 Initializing the Chip-select Registers26813.3.5 Example of a Chip-select Setup26913.4 CHIP CONFIGURATION REGISTERS AND CHIP CONFIGURATION BYTES27113.5 BUS WIDTH AND MULTIPLEXING27513.5.1 A 16-bit Example System27813.5.2 16-bit Bus Timings27913.5.3 8-bit Bus Timings28113.5.4 Comparison of Multiplexed and Demultiplexed Buses28313.6 WAIT STATES (READY CONTROL)28313.7 BUS-HOLD PROTOCOL28713.7.1 Enabling the Bus-hold Protocol28913.7.2 Disabling the Bus-hold Protocol28913.7.3 Hold Latency28913.7.4 Regaining Bus Control29013.8 WRITE-CONTROL MODES29013.9 SYSTEM BUS AC TIMING SPECIFICATIONS29313.9.1 Deferred Bus-cycle Mode (80C196NU Only)29713.9.2 Explanation of AC Symbols29913.9.3 AC Timing Definitions299APPENDIX A INSTRUCTION SET REFERENCE306APPENDIX B SIGNAL DESCRIPTIONS376B.1 FUNCTIONAL GROUPINGS OF SIGNALS376B.2 SIGNAL DESCRIPTIONS381B.3 DEFAULT CONDITIONS388APPENDIX C REGISTERS392GLOSSARY450INDEX460FIGURES35Figure 2-1. 8XC196NP and 80C196NU Block Diagram35Figure 2-2. Block Diagram of the Core36Figure 2-3. Clock Circuitry (8XC196NP)40Figure 2-4. Clock Circuitry (80C196NU)41Figure 2-5. Internal Clock Phases42Figure 2-6. Effect of Clock Mode on CLKOUT Frequency43Figure 3-1. Accumulator (ACC_0 x) Register53Figure 3-2. Accumulator Control and Status (ACC_STAT) Register54Figure 5-1. 16-Mbyte Address Space75Figure 5-2. Pages FFH and 00H76Figure 5-3. Register File Memory Map83Figure 5-4. Windowing86Figure 5-5. Window Selection (WSR) Register87Figure 5-6. Window Selection 1 (WSR1) Register88Figure 5-7. The 24-bit Program Counter96Figure 5-8. Formation of Extended and Nonextended Addresses97Figure 5-9. A 64-Kbyte System With an 8-bit Bus100Figure 5-10. A 64-Kbyte System with Additional Data Storage102Figure 5-11. Example System Using the 1-Mbyte Mode104Figure 6-1. Flow Diagram for PTS and Standard Interrupts109Figure 6-2. Standard Interrupt Response Time116Figure 6-3. PTS Interrupt Response Time116Figure 6-4. PTS Select (PTSSEL) Register118Figure 6-5. Interrupt Mask (INT_MASK) Register119Figure 6-6. Interrupt Mask 1 (INT_MASK1) Register120Figure 6-7. Interrupt Pending (INT_PEND) Register123Figure 6-8. Interrupt Pending 1 (INT_PEND1) Register124Figure 6-9. PTS Control Blocks125Figure 6-10. PTS Service (PTSSRV) Register126Figure 6-11. PTS Mode Selection Bits (PTSCON Bits 7:5)127Figure 6-12. PTS Control Block — Single Transfer Mode128Figure 6-13. PTS Control Block — Block Transfer Mode131Figure 6-14. A Generic PWM Waveform134Figure 6-15. PTS Control Block — PWM Toggle Mode136Figure 6-16. EPA and PTS Operations for the PWM Toggle Mode Example138Figure 6-17. PTS Control Block — PWM Remap Mode141Figure 6-18. EPA and PTS Operations for the PWM Remap Mode Example143Figure 7-1. Bidirectional Port Structure150Figure 7-2. EPORT Block Diagram158Figure 7-3. EPORT Structure160Figure 8-1. SIO Block Diagram168Figure 8-2. Typical Shift Register Circuit for Mode 0171Figure 8-3. Mode 0 Timing172Figure 8-4. Serial Port Frames for Mode 1173Figure 8-5. Serial Port Frames in Mode 2 and 3174Figure 8-6. Serial Port Control (SP_CON) Register176Figure 8-7. Serial Port Baud Rate (SP_BAUD) Register178Figure 8-8. Serial Port Status (SP_STATUS) Register181Figure 9-1. PWM Block Diagram (8XC196NP Only)186Figure 9-2. PWM Block Diagram (80C196NU Only)187Figure 9-3. PWM Output Waveforms190Figure 9-4. Control (CON_REG0) Register192Figure 9-5. PWM Control (PWM x_CONTROL) Register193Figure 9-6. D/A Buffer Block Diagram195Figure 9-7. PWM to Analog Conversion Circuitry195Figure 10-1. EPA Block Diagram199Figure 10-2. EPA Timer/Counters202Figure 10-3. Quadrature Mode Interface204Figure 10-4. Quadrature Mode Timing and Count205Figure 10-5. A Single EPA Capture/Compare Channel206Figure 10-6. EPA Simplified Input-capture Structure207Figure 10-7. Valid EPA Input Events207Figure 10-8. Timer 1 Control (T1CONTROL) Register213Figure 10-9. Timer 2 Control (T2CONTROL) Register214Figure 10-10. EPA Control (EPA x_CON) Registers216Figure 10-11. EPA Interrupt Mask (EPA_MASK) Register219Figure 10-12. EPA Interrupt Pending (EPA_PEND) Register220Figure 11-1. Minimum Hardware Connections230Figure 11-2. Power and Return Connections231Figure 11-3. On-chip Oscillator Circuit232Figure 11-4. External Crystal Connections233Figure 11-5. External Clock Connections234Figure 11-6. External Clock Drive Waveforms234Figure 11-7. Reset Timing Sequence235Figure 11-8. Internal Reset Circuitry236Figure 11-9. Minimum Reset Circuit237Figure 11-10. Example System Reset Circuit237Figure 12-1. Clock Control During Power-saving Modes (8XC196NP)245Figure 12-2. Clock Control During Power-saving Modes (80C196NU)246Figure 12-3. Power-up and Powerdown Sequence When Using an External Interrupt250Figure 12-4. External RC Circuit250Figure 12-5. Typical Voltage on the RPD Pin While Exiting Powerdown252Figure 13-1. Calculation of a Chip-select Output263Figure 13-2. Address Compare (ADDRCOMx) Register264Figure 13-3. Address Mask (ADDRMSK x) Register265Figure 13-4. Bus Control (BUSCON x) Register267Figure 13-5. Example System for Setting Up Chip-select Outputs270Figure 13-6. Chip Configuration 0 (CCR0) Register272Figure 13-7. Chip Configuration 1 (CCR1) Register273Figure 13-8. Multiplexing and Bus Width Options276Figure 13-9. Bus Activity for Four Types of Buses277Figure 13-10. 16-bit External Devices in Demultiplexed Mode279Figure 13-11. Timings for Multiplexed and Demultiplexed 16-bit Buses (8XC196NP)280Figure 13-12. Timings for Multiplexed and Demultiplexed 8-bit Buses (8XC196NP)282Figure 13-13. READY Timing Diagram — Multiplexed Mode285Figure 13-14. READY Timing Diagram — Demultiplexed Mode (8XC196NP)286Figure 13-15. READY Timing Diagram — Demultiplexed Mode (80C196NU)287Figure 13-16. HOLD#, HLDA# Timing288Figure 13-17. Write-control Signal Waveforms291Figure 13-18. Decoding WRL# and WRH#292Figure 13-19. A System with 8-bit and 16-bit Buses293Figure 13-20. Multiplexed System Bus Timing (8XC196NP)294Figure 13-21. Multiplexed System Bus Timing (80C196NU)295Figure 13-22. Demultiplexed System Bus Timing (8XC196NP)296Figure 13-23. Demultiplexed System Bus Timing (80C196NU)297Figure 13-24. Deferred Bus-cycle Mode Timing Diagram (80C196NU)298Figure B-1. 8XC196NP 100-lead SQFP Package377Figure B-2. 8XC196NP 100-lead QFP Package378Figure B-3. 80C196NU 100-lead SQFP Package379Figure B-4. 80C196NU 100-lead QFP Package380TABLES25Table 1-1. Handbooks and Product Information25Table 1-2. Application Notes, Application Briefs, and Article Reprints25Table 1-3. MCS ® 96 Microcontroller Datasheets (Commercial/Express)26Table 1-4. MCS ® 96 Microcontroller Datasheets (Automotive)26Table 1-5. MCS ® 96 Microcontroller Quick References27Table 2-1. Features of the 8XC196NP and 80C196NU35Table 2-2. State Times at Various Frequencies42Table 2-3. Relationships Between Input Frequency, Clock Multiplier, and State Times43Table 3-1. Multiply/Accumulate Example Code51Table 3-2. Effect of SME and FME Bit Combinations55Table 4-1. Operand Type Definitions58Table 4-2. Equivalent Operand Types for Assembly and C Programming Languages59Table 4-3. Definition of Temporary Registers64Table 5-1. 8XC196NP and 80C196NU Memory Map77Table 5-2. Program Memory Access for the 83C196NP78Table 5-3. 8XC196NP and 80C196NU Special-purpose Memory Addresses79Table 5-4. Special-purpose Memory Access for the 83C196NP79Table 5-5. Peripheral SFRs81Table 5-6. Register File Memory Addresses84Table 5-7. CPU SFRs85Table 5-8. Selecting a Window of Peripheral SFRs88Table 5-9. Selecting a Window of the Upper Register File88Table 5-10. Windows90Table 5-11. Windowed Base Addresses91Table 5-12. Memory Map for the System in Figure 5-9101Table 5-13. Memory Map for the System in Figure 5-10103Table 5-14. Memory Map for the System in Figure 5-11105Table 6-1. Interrupt Signals110Table 6-2. Interrupt and PTS Control and Status Registers110Table 6-3. Interrupt Sources, Vectors, and Priorities112Table 6-4. Execution Times for PTS Cycles117Table 6-5. Single Transfer Mode PTSCB130Table 6-6. Block Transfer Mode PTSCB130Table 6-7. Comparison of PWM Modes133Table 6-8. PWM Toggle Mode PTSCB135Table 6-9. PWM Remap Mode PTSCB140Table 7-1. Device I/O Ports146Table 7-2. Bidirectional Port Pins147Table 7-3. Bidirectional Port Control and Status Registers148Table 7-4. Logic Table for Bidirectional Ports in I/O Mode151Table 7-5. Logic Table for Bidirectional Ports in Special-function Mode151Table 7-6. Control Register Values for Each Configuration153Table 7-7. Port Configuration Example153Table 7-8. Port Pin States After Reset and After Example Code Execution154Table 7-9. EPORT Pins156Table 7-10. EPORT Control and Status Registers157Table 7-11. Logic Table for EPORT in I/O Mode161Table 7-12. Logic Table for EPORT in Address Mode161Table 7-13. Configuration Register Settings for EPORT Pins162Table 8-1. Serial Port Signals169Table 8-2. Serial Port Control and Status Registers169Table 8-3. SP_BAUD Values When Using the Internal Clock at 25 MHz179Table 8-4. SP_BAUD Values When Using the Internal Clock at 50 MHz (80C196NU Only)180Table 9-1. PWM Signals187Table 9-2. PWM Control and Status Registers188Table 9-3. PWM Output Frequencies (8XC196NP)191Table 9-4. PWM Output Frequencies (80C196NU)191Table 9-5. PWM Output Alternate Functions194Table 10-1. EPA and Timer/Counter Signals199Table 10-2. EPA Control and Status Registers200Table 10-3. Quadrature Mode Truth Table200Table 10-4. Action Taken when a Valid Edge Occurs208Table 10-5. Example Control Register Settings and EPA Operations215Table 11-1. Minimum Required Signals228Table 11-2. I/O Port Configuration Guide229Table 12-1. Operating Mode Control Signals242Table 12-2. Operating Mode Control and Status Registers243Table 12-3. 80C196NU Clock Modes254Table 13-1. Example of Internal and External Addresses258Table 13-2. External Memory Interface Signals259Table 13-3. Chip-select Registers263Table 13-4. ADDRCOM x Addresses and Reset Values264Table 13-5. ADDRMSK x Addresses and Reset Values265Table 13-6. Base Addresses for Several Sizes of the Address Range266Table 13-7. BUSCON x Addresses and Reset Values268Table 13-8. BUSCON x Registers for the Example System270Table 13-9. Results for the Chip-select Example271Table 13-10. Comparison of AC Timings for Demultiplexed and Multiplexed 16-bit Buses283Table 13-11. READY Signal Timing Definitions284Table 13-12. HOLD#, HLDA# Timing Definitions288Table 13-13. Maximum Hold Latency290Table 13-14. Write Signals for Standard and Write Strobe Modes291Table 13-15. AC Timing Symbol Definitions299Table 13-16. AC Timing Definitions299Table A-1. Opcode Map (Left Half)307Table A-2. Processor Status Word (PSW) Flags309Table A-3. Effect of PSW Flags or Specified Conditions on Conditional Jump Instructions310Table A-4. PSW Flag Setting Symbols310Table A-5. Operand Variables311Table A-6. Instruction Set312Table A-7. Instruction Opcodes352Table A-8. Instruction Lengths and Hexadecimal Opcodes358Table A-9. Instruction Execution Times (in State Times)365Table B-1. 8XC196NP and 80C196NU Signals Arranged by Function376Table B-2. Description of Columns of Table B-3381Table B-3. Signal Descriptions381Table B-4. Definition of Status Symbols388Table B-5. 8XC196NP and 80C196NU Pin Status388Table C-1. Modules and Related Registers392Table C-2. Register Name, Address, and Reset Status393Table C-3. ACC_0 x Addresses and Reset Values396Table C-4. Effect of SME and FME Bit Combinations398Table C-5. ADDRCOMx Addresses and Reset Values399Table C-6. ADDRMSK x Addresses and Reset Values400Table C-7. BUSCON x Addresses and Reset Values401Table C-8. EPA x_CON Addresses and Reset Values414Table C- 9. EPA x_TIME Addresses and Reset Values415Table C-10. P x_DIR Addresses and Reset Values421Table C-11. P x_MODE Addresses and Reset Values422Table C-12. Special-function Signals for Ports 1–4422Table C-13. P x_PIN Addresses and Reset Values423Table C-14. P x_REG Addresses and Reset Values424Table C-15. PWMx_CONTROL Addresses and Reset Values429Table C-16. SP_BAUD Values When Using the Internal Clock at 25 MHz434Table C-17. TIMER x Addresses and Reset Values439Table C-18. WSR Settings and Direct Addresses for Windowable SFRs440Table C-19. WSR1 Settings and Direct Addresses for Windowable SFRs443Größe: 2,9 MBSeiten: 471Language: EnglishHandbuch öffnen
