BenutzerhandbuchInhaltsverzeichnis8XC196Lx Supplement to 8XC196Kx, 8XC196Jx, 87C196CA User’s Manual1Copyright Page2Contents3Figures6Figure 21. 8XC196Lx Block Diagram16Figure 22. Clock Circuitry (87C196LA, LB Only)17Figure 23. Internal Clock Phases (Assumes PLL is ...18Figure 24. Effect of Clock Mode on Internal CLKOU...19Figure 25. Unerasable PROM 1 (USFR1) Register (LA...20Figure 31. Register File Address Map27Figure 41. Interrupt Mask (INT_MASK) Register 37Figure 42. Interrupt Mask 1 (INT_MASK1) Register ...38Figure 43. Interrupt Pending (INT_PEND) Register ...39Figure 44. Interrupt Pending 1 (INT_PEND1) Regist...40Figure 45. PTS Select (PTSSEL) Register41Figure 46. PTS Service (PTSSRV) Register42Table 51. Microcontroller Ports 45Figure 51. Ports 1, 2, 5, and 6 Internal Structur...47Figure 52. Ports 3 and 4 Internal Structure (87C1...50Figure 61. SSIO 0 Clock (SSIO0_CLK) Register 53Figure 62. SSIO 1 Clock (SSIO1_CLK) Register (Con...54Figure 71. EPA Block Diagram (87C196LA, LB Only)60Figure 72. EPA Block Diagram (83C196LD Only)61Figure 73. EPA Interrupt Mask (EPA_MASK) Register...62Figure 74. EPA Interrupt Mask 1 (EPA_MASK1) Regis...62Figure 75. EPA Interrupt Pending (EPA_PEND) Regis...63Figure 76. EPA Interrupt Pending 1 (EPA_PEND1) Re...63Figure 77. EPA Interrupt Priority Vector Register...64Figure 81. Integrated J1850 Communications Protoc...67Figure 82. J1850 Communications Controller Block ...68Figure 83. Huntzicker Symbol Definition for J1850...73Figure 84. Typical VPW Waveform73Figure 85. Bit Arbitration Example74Figure 86. J1850 Message Frames75Figure 87. Huntzicker Symbol Definition for the N...76Figure 88. Definition for Start and End of Frame ...77Figure 89. IFR Type 1 Message Frame78Figure 810. IFR Type 2 Message Frame79Figure 811. IFR Type 3 Message Frame79Figure 812. J1850 Transmitter (J_TX) Register80Figure 813. J1850 Transmit Message Structure80Figure 814. J1850 Receiver (J_RX) Register81Figure 815. J1850 Receive Message Structure81Figure 816. J1850 Command (J_CMD) Register 83Figure 817. J1850 Configuration (J_CFG) Register ...84Figure 818. J1850 Delay (J_DLY) Register86Figure 819. J1850 Status (J_STAT) Register (Conti...87Figure 91. Reset Source (RSTSRC) Register 91Figure 101. Clock Circuitry (87C196LA, LB Only)96Figure 111. Slave Programming Circuit103Figure 112. Serial Port Programming Circuit104Figure A1. 87C196LA 52-pin PLCC Package111Figure A2. 87C196LB 52-pin PLCC Package113Figure A3. 83C196LD 52-pin PLCC Package115Tables8Table 11. Related Documents12Table 21. Features of the 8XC196Lx and 8XC196Kx P...15Table 22. State Times at Various Frequencies18Table 23. Relationships Between Input Frequency, ...19Table 24. UPROM Programming Values and Locations20Table 31. Address Map (Continued)25Table 32. Register File Memory Addresses27Table 33. 8XC196Lx Peripheral SFRs (Continued)28Table 34. Windows (Continued)30Table 41. Interrupt Sources, Vectors, and Priorit...36Table 71. EPA Channels59Table 72. EPA Interrupt Priority Vectors64Table 81. J1850 Controller Signals69Table 82. Control and Status Registers (Continued...69Table 83. Relationships Between Input Frequency, ...72Table 84. Huntzicker Symbol Timing Characteristic...77Table 111. Signature Word and Programming Voltage...101Table 112. 87C196LA, LB OTPROM Address Map 102Table 113. Slave Programming Mode Address Map103Table 114. Serial Port Programming Mode Address M...105Table A1. 87C196LA Signals Arranged by Functional...110Table A2. 87C196LB Signals Arranged by Functional...112Table A3. 83C196LD Signals Arranged by Functional...114Table A4. Definition of Status Symbols 115Table A5. 87C196LA, LB Default Signal Conditions ...116Table A6. 83C196LD Default Signal Conditions 117CHAPTER 1 Guide to This Manual111.1 Manual Contents111.2 Related Documents12CHAPTER 2 Architectural Overview152.1 Microcontroller Features152.2 Block Diagram162.3 Internal Timing162.4 External Timing192.5 Internal Peripherals202.5.1 I/O Ports212.5.2 Synchronous Serial I/O Port212.5.3 Event Processor Array212.5.4 J1850 Communications Controller212.6 Design Considerations21CHAPTER 3 Address Space253.1 Address Partitions253.2 Register File263.3 Peripheral SPecial-Function Registers283.4 Windowing30CHAPTER 4 Standard and PTS Interrupts354.1 Interrupt Sources, Vectors, and Priorities354.2 Interrupt Registers364.2.1 Interrupt Mask Registers374.2.2 Interrupt Pending Registers384.2.3 Peripheral Transaction Server Registers40CHAPTER 5 I/O Ports455.1 I/O Ports Overview455.2 Internal Structure for Ports 1, 2, 5, and 6 (B...455.2.1 Configuring Ports 1, 2, 5, and 6 (Bidirectio...475.2.2 Special Bidirectional Port Considerations485.3 Internal Structure for Ports 3 and 4 (Address/...49CHAPTER 6 Synchronous Serial I/O Port536.1 SSIO 0 Clock Register536.2 SSIO 1 Clock Register54CHAPTER 7 Event Processor Array597.1 EPA Functional Overview597.1.1 EPA Mask Registers627.1.2 EPA Pending Registers637.1.3 EPA Interrupt Priority Vector Register64CHAPTER 8 J1850 Communications Controller678.1 J1850 Functional Overview678.2 J1850 Controller Signals and Registers698.3 J1850 Controller Operation708.3.1 Control State Machine708.3.1.1 Cyclic Redundancy Check Generator708.3.1.2 Bus Contention718.3.1.3 Bit Arbitration718.3.1.4 Error Detection718.3.2 Symbol Synchronization and Timing Circuitry718.3.2.1 Clock Prescaler728.3.2.2 Digital Filter728.3.2.3 Delay Compensation728.3.2.4 Symbol Encoding and Decoding728.3.3 Bit Arbitration Example738.4 Message Frames748.4.1 Standard Messaging758.4.1.1 Header758.4.1.2 CRC Byte758.4.1.3 Normalization Bit758.4.1.4 Start and End Message Frame Symbols768.4.2 In-frame Response Messaging788.4.2.1 IFR Messaging Type 1: Single Byte, Single ...788.4.2.2 IFR Messaging Type 2: Single Byte, Multipl...788.4.2.3 IFR Messaging Type 3: Multiple Bytes, Sing...798.5 Transmitting and Receiving Messages798.5.1 Transmitting Messages798.5.2 Receiving Messages818.5.3 IFR Messages828.6 Programming the J1850 Controller828.6.1 Programming the J1850 Command (J_CMD) Regist...828.6.2 Programming the J1850 Configuration (J_CFG) ...848.6.3 Programming the J1850 Delay Compensation (J_...858.6.4 Programming the J1850 Status (J_STAT) Regist...87CHAPTER 9 Minimum Hardware Considerations919.1 Identifying the Reset Source919.2 Design Considerations for 8XC196LA, LB, and LD...92CHAPTER 10 Special Operating Modes9510.1 Internal Timing9510.2 Entering and Exiting ONCE Mode96CHAPTER 11 Programming the Nonvolatile Memory10111.1 Signature Word and Programming Voltage Values...10111.2 OTPROM Address Map10111.3 Slave Programming Circuit and Address Map10211.4 Serial Port Programming Circuit and Address M...104APPENDIX A Signal Descriptions109A.1 Functional Groupings of Signals109A.2 Default Conditions115Größe: 2,7 MBSeiten: 136Language: EnglishHandbuch öffnen
