Datenbogen (AT80571PG0642ML)InhaltsverzeichnisIntel® Pentium® Dual-Core Processor E6000D and E5000D Series1Contents3Figures5Tables6Intel® Pentium® Dual-Core Processor E6000 and E5000 Series Features7Revision History81 Introduction91.1 Terminology91.1.1 Processor Terminology Definitions101.2 References11Table 1. References112 Electrical Specifications132.1 Power and Ground Lands132.2 Decoupling Guidelines132.2.1 VCC Decoupling132.2.2 VTT Decoupling132.2.3 FSB Decoupling142.3 Voltage Identification14Table 2. Voltage Identification Definition152.4 Reserved, Unused, and TESTHI Signals162.5 Power Segment Identifier (PSID)162.6 Voltage and Current Specification172.6.1 Absolute Maximum and Minimum Ratings17Table 3. Absolute Maximum and Minimum Ratings172.6.2 DC Voltage and Current Specification18Table 4. Voltage and Current Specifications18Table 5. Processor VCC Static and Transient Tolerance19Figure 1. Processor VCC Static and Transient Tolerance202.6.3 VCC Overshoot20Table 6. VCC Overshoot Specifications20Figure 2. VCC Overshoot Example Waveform212.6.4 Die Voltage Validation212.7 Signaling Specifications212.7.1 FSB Signal Groups22Table 7. FSB Signal Groups22Table 8. Signal Characteristics23Table 9. Signal Reference Voltages232.7.2 CMOS and Open Drain Signals232.7.3 Processor DC Specifications24Table 10. GTL+ Signal Group DC Specifications24Table 11. Open Drain and TAP Output Signal Group DC Specifications24Table 12. CMOS Signal Group DC Specifications252.7.3.1 Platform Environment Control Interface (PECI) DC Specifications25Table 13. PECI DC Electrical Limits262.7.3.2 GTL+ Front Side Bus Specifications26Table 14. GTL+ Bus Voltage Definitions272.8 Clock Specifications272.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking27Table 15. Core Frequency to FSB Multiplier Configuration282.8.2 FSB Frequency Select Signals (BSEL[2:0])28Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]292.8.3 Phase Lock Loop (PLL) and Filter292.8.4 BCLK[1:0] Specifications29Table 17. Front Side Bus Differential BCLK Specifications29Table 18. FSB Differential Clock Specifications (800 MHz FSB)30Table 19. FSB Differential Clock Specifications (1066 MHz FSB)30Figure 3. Differential Clock Waveform31Figure 4. Measurement Points for Differential Clock Waveforms313 Package Mechanical Specifications33Figure 5. Processor Package Assembly Sketch333.1 Package Mechanical Drawing33Figure 6. Processor Package Drawing Sheet 1 of 334Figure 7. Processor Package Drawing Sheet 2 of 335Figure 8. Processor Package Drawing Sheet 3 of 3363.2 Processor Component Keep-Out Zones373.3 Package Loading Specifications37Table 20. Processor Loading Specifications373.4 Package Handling Guidelines37Table 21. Package Handling Guidelines373.5 Package Insertion Specifications383.6 Processor Mass Specification383.7 Processor Materials38Table 22. Processor Materials383.8 Processor Markings38Figure 9. Intel® Pentium® Dual-Core Processor E5000 Series Top-Side Markings Example38Figure 10. Intel® Pentium® Dual-Core Processor E6000 Series Top-Side Markings Example393.9 Processor Land Coordinates40Figure 11. Processor Land Coordinates and Quadrants, Top View404 Land Listing and Signal Descriptions414.1 Processor Land Assignments41Figure 12. land-out Diagram (Top View – Left Side)42Figure 13. land-out Diagram (Top View – Right Side)43Table 23. Alphabetical Land Assignments44Table 24. Numerical Land Assignment544.2 Alphabetical Signals Reference64Table 25. Signal Description (Sheet 1 of 10)645 Thermal Specifications and Design Considerations755.1 Processor Thermal Specifications755.1.1 Thermal Specifications75Table 26. Processor Thermal Specifications76Table 27. Processor Thermal Profile77Figure 14. Processor Series Thermal Profile775.1.2 Thermal Metrology78Figure 15. Case Temperature (TC) Measurement Location785.2 Processor Thermal Features785.2.1 Thermal Monitor785.2.2 Thermal Monitor 279Figure 16. Thermal Monitor 2 Frequency and Voltage Ordering805.2.3 On-Demand Mode805.2.4 PROCHOT# Signal815.2.5 THERMTRIP# Signal815.3 Platform Environment Control Interface (PECI)825.3.1 Introduction825.3.1.1 TCONTROL and TCC activation on PECI-Based Systems82Figure 17. Conceptual Fan Control Diagram on PECI-Based Platforms825.3.2 PECI Specifications835.3.2.1 PECI Device Address835.3.2.2 PECI Command Support835.3.2.3 PECI Fault Handling Requirements835.3.2.4 PECI GetTemp0() Error Code Support83Table 28. GetTemp0() Error Codes836 Features856.1 Power-On Configuration Options85Table 29. Power-On Configuration Option Signals856.2 Clock Control and Low Power States85Figure 18. Processor Low Power State Machine866.2.1 Normal State866.2.2 HALT and Extended HALT Powerdown States866.2.2.1 HALT Powerdown State866.2.2.2 Extended HALT Powerdown State876.2.3 Stop Grant and Extended Stop Grant States876.2.3.1 Stop-Grant State876.2.3.2 Extended Stop Grant State886.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State886.2.4.1 HALT Snoop State, Stop Grant Snoop State886.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State886.2.5 Sleep State886.2.6 Deep Sleep State896.2.7 Deeper Sleep State896.2.8 Enhanced Intel SpeedStep® Technology906.3 Processor Power Status Indicator (PSI) Signal907 Boxed Processor Specifications917.1 Introduction91Figure 19. Mechanical Representation of the Boxed Processor917.2 Mechanical Specifications927.2.1 Boxed Processor Cooling Solution Dimensions92Figure 20. Space Requirements for the Boxed Processor (Side View)92Figure 21. Space Requirements for the Boxed Processor (Top View)92Figure 22. Overall View Space Requirements for the Boxed Processor937.2.2 Boxed Processor Fan Heatsink Weight937.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly937.3 Electrical Requirements937.3.1 Fan Heatsink Power Supply93Figure 23. Boxed Processor Fan Heatsink Power Cable Connector Description94Table 30. Fan Heatsink Power and Signal Specifications94Figure 24. Baseboard Power Header Placement Relative to Processor Socket957.4 Thermal Specifications957.4.1 Boxed Processor Cooling Requirements95Figure 25. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)96Figure 26. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)967.4.2 Variable Speed Fan97Figure 27. Boxed Processor Fan Heatsink Set Points97Table 31. Fan Heatsink Power and Signal Specifications988 Debug Tools Specifications998.1 Logic Analyzer Interface (LAI)998.1.1 Mechanical Considerations998.1.2 Electrical Considerations99Größe: 1,56 MBSeiten: 100Language: EnglishHandbuch öffnen
Datenbogen (BX80571E5300)InhaltsverzeichnisIntel® Pentium® Dual-Core Processor E5000D Series1Contents3Figures5Tables6Intel® Pentium® Dual-Core Processor E5000 Series Features7Revision History81 Introduction91.1 Terminology91.1.1 Processor Terminology Definitions101.2 References11Table 1. References112 Electrical Specifications132.1 Power and Ground Lands132.2 Decoupling Guidelines132.2.1 VCC Decoupling132.2.2 VTT Decoupling132.2.3 FSB Decoupling142.3 Voltage Identification14Table 2. Voltage Identification Definition152.4 Reserved, Unused, and TESTHI Signals162.5 Power Segment Identifier (PSID)162.6 Voltage and Current Specification172.6.1 Absolute Maximum and Minimum Ratings17Table 3. Absolute Maximum and Minimum Ratings172.6.2 DC Voltage and Current Specification18Table 4. Voltage and Current Specifications18Table 5. Processor VCC Static and Transient Tolerance19Figure 1. Processor VCC Static and Transient Tolerance202.6.3 VCC Overshoot20Table 6. VCC Overshoot Specifications20Figure 2. VCC Overshoot Example Waveform212.6.4 Die Voltage Validation212.7 Signaling Specifications212.7.1 FSB Signal Groups22Table 7. FSB Signal Groups22Table 8. Signal Characteristics23Table 9. Signal Reference Voltages232.7.2 CMOS and Open Drain Signals232.7.3 Processor DC Specifications24Table 10. GTL+ Signal Group DC Specifications24Table 11. Open Drain and TAP Output Signal Group DC Specifications24Table 12. CMOS Signal Group DC Specifications252.7.3.1 Platform Environment Control Interface (PECI) DC Specifications25Table 13. PECI DC Electrical Limits262.7.3.2 GTL+ Front Side Bus Specifications26Table 14. GTL+ Bus Voltage Definitions272.8 Clock Specifications272.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking27Table 15. Core Frequency to FSB Multiplier Configuration282.8.2 FSB Frequency Select Signals (BSEL[2:0])28Table 16. BSEL[2:0] Frequency Table for BCLK[1:0]292.8.3 Phase Lock Loop (PLL) and Filter292.8.4 BCLK[1:0] Specifications29Table 17. Front Side Bus Differential BCLK Specifications29Table 18. FSB Differential Clock Specifications (800 MHz FSB)30Figure 3. Differential Clock Waveform30Figure 4. Measurement Points for Differential Clock Waveforms313 Package Mechanical Specifications33Figure 5. Processor Package Assembly Sketch333.1 Package Mechanical Drawing33Figure 6. Processor Package Drawing Sheet 1 of 334Figure 7. Processor Package Drawing Sheet 2 of 335Figure 8. Processor Package Drawing Sheet 3 of 3363.2 Processor Component Keep-Out Zones373.3 Package Loading Specifications37Table 19. Processor Loading Specifications373.4 Package Handling Guidelines37Table 20. Package Handling Guidelines373.5 Package Insertion Specifications383.6 Processor Mass Specification383.7 Processor Materials38Table 21. Processor Materials383.8 Processor Markings38Figure 9. Processor Top-Side Markings Example383.9 Processor Land Coordinates39Figure 10. Processor Land Coordinates and Quadrants, Top View394 Land Listing and Signal Descriptions414.1 Processor Land Assignments41Figure 11. land-out Diagram (Top View - Left Side)42Figure 12. land-out Diagram (Top View - Right Side)43Table 22. Alphabetical Land Assignments44Table 23. Numerical Land Assignment544.2 Alphabetical Signals Reference64Table 24. Signal Description (Sheet 10 of 10)645 Thermal Specifications and Design Considerations755.1 Processor Thermal Specifications755.1.1 Thermal Specifications75Table 25. Processor Thermal Specifications76Table 26. Processor Thermal Profile77Figure 13. Processor Series Thermal Profile775.1.2 Thermal Metrology78Figure 14. Case Temperature (TC) Measurement Location785.2 Processor Thermal Features785.2.1 Thermal Monitor785.2.2 Thermal Monitor 279Figure 15. Thermal Monitor 2 Frequency and Voltage Ordering805.2.3 On-Demand Mode805.2.4 PROCHOT# Signal805.2.5 THERMTRIP# Signal815.3 Platform Environment Control Interface (PECI)815.3.1 Introduction815.3.1.1 TCONTROL and TCC activation on PECI-Based Systems82Figure 16. Conceptual Fan Control Diagram on PECI-Based Platforms825.3.2 PECI Specifications825.3.2.1 PECI Device Address825.3.2.2 PECI Command Support825.3.2.3 PECI Fault Handling Requirements835.3.2.4 PECI GetTemp0() Error Code Support83Table 27. GetTemp0() Error Codes836 Features856.1 Power-On Configuration Options85Table 28. Power-On Configuration Option Signals856.2 Clock Control and Low Power States85Figure 17. Processor Low Power State Machine866.2.1 Normal State866.2.2 HALT and Extended HALT Powerdown States866.2.2.1 HALT Powerdown State866.2.2.2 Extended HALT Powerdown State876.2.3 Stop Grant and Extended Stop Grant States876.2.3.1 Stop-Grant State876.2.3.2 Extended Stop Grant State886.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State886.2.4.1 HALT Snoop State, Stop Grant Snoop State886.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State886.2.5 Sleep State886.2.6 Deep Sleep State896.2.7 Deeper Sleep State896.2.8 Enhanced Intel SpeedStep® Technology906.3 Processor Power Status Indicator (PSI) Signal907 Boxed Processor Specifications917.1 Introduction91Figure 18. Mechanical Representation of the Boxed Processor917.2 Mechanical Specifications927.2.1 Boxed Processor Cooling Solution Dimensions92Figure 19. Space Requirements for the Boxed Processor (Side View)92Figure 20. Space Requirements for the Boxed Processor (Top View)92Figure 21. Overall View Space Requirements for the Boxed Processor937.2.2 Boxed Processor Fan Heatsink Weight937.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly937.3 Electrical Requirements937.3.1 Fan Heatsink Power Supply93Figure 22. Boxed Processor Fan Heatsink Power Cable Connector Description94Table 29. Fan Heatsink Power and Signal Specifications94Figure 23. Baseboard Power Header Placement Relative to Processor Socket957.4 Thermal Specifications957.4.1 Boxed Processor Cooling Requirements95Figure 24. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)96Figure 25. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 2 view)967.4.2 Variable Speed Fan97Figure 26. Boxed Processor Fan Heatsink Set Points97Table 30. Fan Heatsink Power and Signal Specifications988 Debug Tools Specifications998.1 Logic Analyzer Interface (LAI)998.1.1 Mechanical Considerations998.1.2 Electrical Considerations99Größe: 1,35 MBSeiten: 100Language: EnglishHandbuch öffnen
