Benutzerhandbuch für Intel I/O Processor

Inhaltsverzeichnis

• Intel® IQ80332 I/O Processor

  1
• Introduction 1

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  • 1.1 Document Purpose and Scope

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  • 1.2 Other Related Documents

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    • Table 1. Intel® 80332 I/O Processor Related Documentation List

      9
  • 1.3 Electronic Information

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    • Table 2. Electronic Information

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  • 1.4 Component References

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    • Table 3. Component Reference

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  • 1.5 Terms and Definitions

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    • Table 4. Terms and Definitions

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  • 1.6 Intel® 80332 I/O Processor

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    • Figure 1. Intel® 80332 I/O Processor Block Diagram

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  • 1.7 Intel® IQ80332 I/O Processor Evaluation Platform Board Features

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    • Table 5. Summary of Features

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• Getting Started 2

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  • 2.1 Kit Content

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  • 2.2 Hardware Installation

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    • 2.2.1 First-Time Installation and Test

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    • 2.2.2 Power Requirements

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  • 2.3 Factory Settings

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  • 2.4 Development Strategy

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    • 2.4.1 Supported Tool Buckets

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    • 2.4.2 Contents of the Flash

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  • 2.5 Target Monitors

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    • 2.5.1 RedHat RedBoot

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  • 2.6 Host Communications Examples

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    • 2.6.1 Serial-UART Communication

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      • Figure 2. Serial-UART Communication

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    • 2.6.2 JTAG Debug Communication

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      • Figure 3. JTAG Debug Communication

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    • 2.6.3 Network Communication

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      • Figure 4. Network Communication Example

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    • 2.6.4 GNUPro GDB/Insight

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      • 2.6.4.1 Communicating with RedBoot

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      • 2.6.4.2 Connecting with GDB

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• Hardware Reference Section 3

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  • 3.1 Functional Diagram

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    • Figure 5. Functional Block Diagram

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  • 3.2 Board Form-Factor/Connectivity

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    • Table 6. Form-Factor/Connectivity Features

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    • Figure 6. Board Form Factor

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  • 3.3 Power

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    • Table 7. Power Features

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  • 3.4 Memory Subsystem

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    • 3.4.1 DDR SDRAM

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      • 3.4.1.1 Battery Backup

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    • 3.4.2 Flash Memory Requirements

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      • Table 8. Flash Memory Requirements

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  • 3.5 Interrupt Routing

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    • Table 9. External Interrupt Routing to Intel® 80332 I/O Processor

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  • 3.6 Intel® IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus

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    • Figure 7. Intel® IQ80332 I/O Processor Evaluation Platform Board Peripheral Bus Topology

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    • Table 10. Peripheral Bus Features

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    • 3.6.1 Flash ROM

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      • Table 11. Flash ROM Features

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      • Figure 8. Flash Connection on Peripheral Bus

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    • 3.6.2 UART

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    • 3.6.3 Non-Volatile RAM

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    • 3.6.4 Audio Buzzer

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    • 3.6.5 HEX Display

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    • 3.6.6 Rotary Switch

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      • Table 12. Rotary Switch Requirements

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    • 3.6.7 Battery Status

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      • Table 13. Battery Status Buffer Requirements

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  • 3.7 Debug Interface

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    • 3.7.1 Console Serial Port

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    • 3.7.2 JTAG Debug

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      • 3.7.2.1 JTAG Port

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        • Figure 9. JTAG Port Pin-out

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  • 3.8 Board Reset Scheme

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    • Table 14. Reset Requirements/Schemes

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    • Figure 10. RESET Sources

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  • 3.9 Switches and Jumpers

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    • 3.9.1 Switch Summary

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      • Table 15. Switch Summary

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    • 3.9.2 Default Switch Settings of S7A1- Visual

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      • Table 16. Switch S7A1

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      • Figure 11. Default Switch Setting Switch S7A1

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    • 3.9.3 Jumper Summary

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      • Table 17. Jumper Summary

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    • 3.9.4 Connector Summary

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      • Table 18. Connector Summary

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    • 3.9.5 General Purpose Input/Output Header

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      • Table 19. J2D2 GPIO Header Definition

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    • 3.9.6 Detail Descriptions of Switches/Jumpers

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      • 3.9.6.1 Switch S1C2: 80332 Reset

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      • 3.9.6.2 Switch S6A1: BPCI-X Reset

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      • 3.9.6.3 Switch S8A1: Rotary

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        • Table 20. Rotary Switch Settings

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      • 3.9.6.4 Switch S7A1

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        • 3.9.6.4.1 S7A1-1: PCI-X Bus A Speed Enable corresponding to signal name PBI_AD3

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          • Table 21. S7A1-1: PCI-X Bus A Speed Enable

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        • 3.9.6.4.2 S7A1-2: Reset IOP core corresponding to signal name PBI_AD5

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          • Table 22. Switch S7A1-2: Reset IOP: Settings and Operation Mode

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        • 3.9.6.4.3 S7A1-3: Configration Cycle Enable corresponding to signal name PBI_AD6

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          • Table 23. Switch S7A1-3: RETRY: Settings and Operation Mode

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        • 3.9.6.4.4 S7A1-4: PCI-X Bus B Speed Enable corresponding to signal name PBI_AD10

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          • Table 24. S7A1-4: PCI-X Bus B Speed Enable: Settings and Operation Mode

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        • 3.9.6.4.5 S7A1-5: PCI-X Bus B Hot-Plug Reset Disable corresponding to signal name PBI_AD11

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          • Table 25. S7A1-5: PCI-X Bus B Hot-Plug Reset Disable: Settings and Operation Mode

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        • 3.9.6.4.6 Switch S7A1- 6: Hot Plug Capable Disabled corresponding to signal name PBI_AD15

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          • Table 26. Switch S7A1- 6: Hot Plug Capable Disabled: Settings and Operation Mode

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        • 3.9.6.4.7 Switch S7A1 - 7: SMBUS Manageability Address Bit 0 corresponding to signal name PBI_AD17

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          • Table 27. Switch S7A1 - 7: SMBUS Manageability Address Bit 0: Settings and Operation Mode

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        • 3.9.6.4.8 Switch S7A1 - 8: SMBUS Manageability Address Bit 3 corresponding to signal name PBI_AD18

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          • Table 28. Switch S7A1 - 8: SMBUS Manageability Address Bit 3: Settings and Operation Mode

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        • 3.9.6.4.9 Switch S7A1- 9:SMBUS Manageability Address Bit 2 corresponding to signal name PBI_AD17

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          • Table 29. Switch S7A1 - 9: SMBUS Manageability Address Bit 2: Settings and Operation Mode

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        • 3.9.6.4.10 Switch S7A1- 10: SMBUS Manageability Address Bit 1 corresponding to signal name PBI_AD16

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          • Table 30. Switch S7A1 - 10: SMBUS Slave Address 0: Settings and Operation Mode

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      • 3.9.6.5 Jumper J7D1: Flash bit-width

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        • Table 31. Jumper J7D1: Descriptions

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        • Table 32. Jumper J7D1: Settings and Operation Mode

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      • 3.9.6.6 Jumper J1C1: JTAG Chain

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        • Table 33. Jumper J1C1: Descriptions

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        • Table 34. Jumper J1C1: Settings and Operation Mode

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      • 3.9.6.7 Jumper J1D2: UART Control

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        • Table 35. Jumper J1D2: Descriptions

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        • Table 36. Jumper J1D2: Settings and Operation Mode

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      • 3.9.6.8 Jumper J7B4: SMBus Header

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        • Table 37. Jumper J7B4: Descriptions

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        • Table 38. Jumper J7B4: Settings and Operation Mode

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      • 3.9.6.9 Jumper J9D3: Buzzer Volume Control

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        • Table 39. Jumper J9D3: Descriptions

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        • Table 40. Jumper J9D3: Settings and Operation Mode

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• Software Reference 4

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  • 4.1 DRAM

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  • 4.2 Components on the Peripheral Bus

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    • 4.2.1 Flash ROM

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      • Figure 12. Flash Connection to Peripheral Bus

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    • 4.2.2 Peripheral Bus Memory Map

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      • Table 41. Peripheral Bus Memory Map

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  • 4.3 Board Support Package (BSP) Examples

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    • 4.3.1 Intel® 80332 I/O Processor Memory Map

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      • Figure 13. Intel® 80332 I/O Processor Memory Map

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    • 4.3.2 RedBoot* Intel® 80332 I/O Processor Memory Map

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    • 4.3.3 RedBoot Intel® 80332 I/O Processor Files

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    • 4.3.4 RedBoot 80332 DDR Memory Initialization Sequence

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• IQ80321 and IQ80332 Comparisons A

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  • Table 42. Intel® IQ80321 Evaluation Platform Board and Intel® IQ80332 I/O processor evaluation platform board Comparisons

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• Getting Started and Debugger B

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  • B.1 Introduction

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    • B.1.1 Purpose

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    • B.1.2 Necessary Hardware and Software

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    • B.1.3 Related Documents

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      • Table 43. Related Documents

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    • B.1.4 Related Web Sites

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  • B.2 Setup

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    • B.2.1 Hardware Setup

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      • Figure 14. Intel® 80332 I/O Processor Hardware Setup Flow Chart

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    • B.2.2 Software Setup

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      • Figure 15. Software Flow Diagram

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  • B.3 New Project Setup

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    • B.3.1 Creating a New Project

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    • B.3.2 Configuration

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  • B.4 Flashing with JTAG

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    • B.4.1 Overview

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    • B.4.2 Using Flash Programmer

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  • B.5 Debugging Out of Flash

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  • B.6 Building an Executable File From Example Code

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  • B.7 Running the Code|Lab Debugger

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    • B.7.1 Launching and Configuring Debugger

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    • B.7.2 Manually Loading and Executing an Application Program

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    • B.7.3 Displaying Source Code

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    • B.7.4 Using Breakpoints

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    • B.7.5 Stepping Through the Code

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    • B.7.6 Setting Code|Lab Debug Options

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  • B.8 Exploring the Code|Lab Debug Windows

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    • B.8.1 Toolbar Icons

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    • B.8.2 Workspace Window

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    • B.8.3 Source Code

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    • B.8.4 4 Debug and Console Windows

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    • B.8.5 Memory Window

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    • B.8.6 Registers Window

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    • B.8.7 Watch Window

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    • B.8.8 Variables Window

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  • B.9 Debugging Basics

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    • B.9.1 Overview

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    • B.9.2 Hardware and Software Breakpoints

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      • B.9.2.1 Software Breakpoints

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      • B.9.2.2 Hardware Breakpoints

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    • B.9.3 C.9.3 Exceptions/Trapping

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