Benutzerhandbuch für Intel IQ80321

Inhaltsverzeichnis

• Intel® IQ80321 I/O Processor Evaluation Platform

  1
• Introduction 1

  13
  • 1.1 Document Purpose and Scope

    13
  • 1.2 Related Documents

    13
    • Table 1. Intel® 80321 I/O Processor Related Documentation List

      13
  • 1.3 Electronic Information

    14
    • Table 2. Electronic Information 

      14
  • 1.4 Component References

    14
    • Table 3. Component Reference

      14
  • 1.5 Terms and Definitions

    15
    • Table 4. Terms and Definitions

      15
  • 1.6 Intel® 80321 I/O Processor

    16
    • Figure 1. Intel® 80321 I/O Processor Block Diagram

      16
  • 1.7 Intel® IQ80321 Evaluation Platform Board Features

    18
    • Table 5. Summary of Features

      18
• Getting Started 2

  19
  • 2.1 Kit Content

    19
  • 2.2 Hardware Installation

    19
    • 2.2.1 First-Time Installation and Test

      19
    • 2.2.2 Power and Backplane Requirements

      19
  • 2.3 Factory Settings

    20
  • 2.4 Development Strategy

    20
    • 2.4.1 Supported Tool Buckets

      20
    • 2.4.2 Contents of the Flash

      20
  • 2.5 Target Monitors

    21
    • 2.5.1 Redhat Redboot

      21
    • 2.5.2 ARM Firmware Suite

      22
      • 2.5.2.1 ARM Angel

        23
        • 2.5.2.1.1 Semihosting (File I/O)

          23
  • 2.6 Host Communications Examples

    24
    • 2.6.1 Serial-UART Communication

      24
      • Figure 2. Serial-UART Communication

        24
    • 2.6.2 Ethernet-Network Communication

      24
      • Figure 3. Ethernet-Network Communication

        24
    • 2.6.3 JTAG Debug Communication

      25
      • Figure 4. JTAG Debug Communication

        25
    • 2.6.4 GNUPro GDB/Insight

      26
      • 2.6.4.1 Communicating with Redboot

        26
      • 2.6.4.2 Connecting with GDB

        28
    • 2.6.5 ARM Extended Debugger

      29
• Hardware Reference Section 3

  31
  • 3.1 Functional Diagram

    31
    • Figure 5. Functional Block Diagram

      31
  • 3.2 Board Form-Factor/Connectivity

    32
    • Table 6. Form-Factor/Connectivity Features

      32
    • Figure 6. Board Form Factor

      32
  • 3.3 Power

    33
    • Table 7. Power Features

      33
  • 3.4 Memory Subsystem

    34
    • 3.4.1 DDR SDRAM

      34
      • Table 8. DDR Memory Features

        34
      • Table 9. Supported DIMM Types

        34
      • 3.4.1.1 Battery Backup

        34
    • 3.4.2 Flash Memory Requirements

      35
      • Table 10. Flash Memory Requirements

        35
  • 3.5 Intel® 80321 I/O Processor Operation Mode

    36
  • 3.6 Interrupt Routing

    37
    • Figure 7. External Interrupt Routing to Intel® 80321 I/O Processor

      37
  • 3.7 Intel® IQ80321 Evaluation Platform Board Peripheral Bus

    38
    • Figure 8. Intel® IQ80321 Evaluation Platform Board Peripheral Bus Topology

      38
    • Table 11. Peripheral Bus Features

      38
    • 3.7.1 Flash ROM

      39
      • Table 12. Flash ROM Features

        39
      • Figure 9. Flash Connection on Peripheral Bus

        39
    • 3.7.2 UART

      40
      • Table 13. UART Features

        40
      • Figure 10. UART Connection on the Peripheral Bus

        40
    • 3.7.3 HEX Display

      41
      • Table 14. HEX Display on the Peripheral Bus

        41
      • Figure 11. HEX Display Connection on the Peripheral Bus

        41
    • 3.7.4 Rotary Switch

      42
      • Table 15. Rotary Switch Requirements

        42
      • Figure 12. Rotary Switch Connection on the Peripheral Bus

        42
    • 3.7.5 Battery Status

      43
      • Table 16. Battery Status Buffer Requirements

        43
      • Figure 13. Battery Status Buffer on Peripheral Bus

        43
  • 3.8 Debug Interface

    44
    • 3.8.1 Console Serial Port

      44
    • 3.8.2 Ethernet Port

      44
      • 3.8.2.1 Intel® 82544EI Gigabit Ethernet Controller

        44
    • 3.8.3 JTAG Debug

      45
      • 3.8.3.1 JTAG Port

        45
        • Figure 14. JTAG Port Pin-out

          45
    • 3.8.4 Logic-Analyzer Connectors

      45
      • Table 17. Logic Analyzer Connection

        45
    • 3.8.5 Mictor J3F2

      46
      • Table 18. Micor J3F2 Signal/Pins

        46
    • 3.8.6 Mictor J2F1

      47
      • Table 19. Micor J2F1 Signal/Pins

        47
    • 3.8.7 Mictor J1C1

      48
      • Table 20. Micor J1C1 Signal/Pins

        48
    • 3.8.8 Mictor J3C1

      49
      • Table 21. Micor J3C1 Signal/Pins

        49
    • 3.8.9 Mictor J2C1

      50
      • Table 22. Micor J2C1 Signal/Pins

        50
  • 3.9 Board Reset Scheme

    51
    • Table 23. Reset Requirements/Schemes

      51
    • Figure 15. RESET Sources

      51
  • 3.10 Switches and Jumpers

    52
    • 3.10.1 Switch Summary

      52
      • Table 24. Switch Summary

        52
    • 3.10.2 PCIX Initialization Summary

      53
      • Figure 16. PCI-X Routing Diagram on Secondary PCI-X Bridge

        53
      • 3.10.2.1 User Defined Switches

        53
      • 3.10.2.2 PCI-X Bridge Initialization Signals

        53
    • 3.10.3 Default Switch Settings - Visual

      54
      • Table 25. Switch S7E1

        54
      • Table 26. Switch S8E1

        54
      • Table 27. Switch S8E2

        54
      • Table 28. Switch S9E1

        54
      • Table 29. Switch S1D1

        54
      • Table 30. Switch S4D1

        54
    • 3.10.4 Jumper Summary

      55
      • Table 31. Jumper Summary

        55
    • 3.10.5 Connector Summary

      55
      • Table 32. Connector Summary

        55
    • 3.10.6 General Purpose Input/Output Header

      55
      • Table 33. GPIO Header (J3F1) Definition

        55
    • 3.10.7 Secondary PCI/PCI-X Operation Settings

      56
      • Table 34. Secondary PCI/PCI-X Operation Settings

        56
    • 3.10.8 Primary PCI/PCI-X Operation Settings

      56
      • Table 35. Primary PCI/PCI-X Operation Settings

        56
    • 3.10.9 Detail Descriptions of Switches/Jumpers

      57
      • 3.10.9.1 Switch S7E1- 2/3

        57
        • Table 36. Switch S7E1- 2/3: General Descriptions

          57
        • 3.10.9.1.1 S7E1-2: RST_MODE

          57
          • Table 37. Switch S7E1-2: RST_MODE: Settings and Operation Mode

            57
        • 3.10.9.1.2 S7E1-3: RETRY

          57
          • Table 38. Switch S7E1-3: RETRY: Settings and Operation Mode

            57
        • 3.10.9.1.3 Operation Setting Summary Descriptions

          57
          • Table 39. RST_MODE and RETRY Operation Setting Summary

            57
      • 3.10.9.2 Switch S7E1- 4/5

        58
        • Table 40. Switch S7E1 - 4/5: Descriptions

          58
        • 3.10.9.2.1 Switch S7E1 - 4

          58
          • Table 41. Switch S7E1 - 4: Settings and Operation Mode

            58
        • 3.10.9.2.2 Switch S7E1 - 5

          58
          • Table 42. Switch S7E1 - 5: Settings and Operation Mode

            58
      • 3.10.9.3 Switch S7E1- 6/7

        58
        • Table 43. Switch S7E1 - 6/7: Descriptions

          58
        • Table 44. Switch S7E1 - 6/7: Settings and Operation Mode

          58
      • 3.10.9.4 Switch S7E1- 8

        59
        • Table 45. Switch S7E1 - 8: Descriptions

          59
        • Table 46. Switch S7E1 - 8: Settings and Operation Mode

          59
      • 3.10.9.5 Switch S8E1- 2

        60
        • Table 47. Switch S8E1 - 2: Descriptions

          60
        • Table 48. Switch S8E1 - 2: Settings and Operation Mode

          60
      • 3.10.9.6 Switch S8E1- 3

        60
        • Table 49. Switch S8E1 - 3: Descriptions

          60
        • Table 50. Switch S8E1 - 3: Settings and Operation Mode

          60
      • 3.10.9.7 Switch S8E1- 4

        60
        • Table 51. Switch S8E1 - 4: Descriptions

          60
        • Table 52. Switch S8E1 - 4: Settings and Operation Mode

          60
      • 3.10.9.8 Switch S8E1- 5

        61
        • 3.10.9.8.1 Switch S8E1 - 5: Descriptions

          61
          • Table 53. Switch S8E1 - 5: Settings and Operation Mode

            61
          • Table 54. Switch S8E1 - 5: Driver Mode Output Impedances

            61
      • 3.10.9.9 Switch S8E1- 6

        61
        • Table 55. Switch S8E1 - 6: Descriptions

          61
        • Table 56. Switch S8E1 - 6: Settings and Operation Mode

          61
        • Table 57. Switch S8E1 - 6: Driver Mode Output Impedances

          61
      • 3.10.9.10 Switch S8E1- 7

        62
        • Table 58. Switch S8E1 - 7: Descriptions

          62
        • Table 59. Switch S8E1 - 7: Settings and Operation Mode

          62
      • 3.10.9.11 Switch S8E1- 8

        62
        • Table 60. Switch S8E1 - 8: Descriptions

          62
        • Table 61. Switch S8E1 - 8: Settings and Operation Mode

          62
      • 3.10.9.12 Switch S8E2 - 1/2

        63
        • Table 62. Switch S8E2 - 1/2: Descriptions

          63
        • Table 63. Switch S8E2 - 1/2: Settings and Operation Mode

          63
      • 3.10.9.13 Switch S8E2 - 4

        63
        • Table 64. Switch S8E2 - 4: Descriptions

          63
        • Table 65. Switch S8E2 - 4: Settings and Operation Mode

          63
      • 3.10.9.14 Switch S9E1 - 1:3

        64
        • Table 66. Switch S9E1 - (1:3) Descriptions

          64
        • Table 67. Switch S9E1 - (1:3) Settings and Operation Mode

          64
      • 3.10.9.15 Switch S9E1 - 4

        64
        • Table 68. Switch S9E1 - 4: Descriptions

          64
        • Table 69. Switch S9E1 - 4: Settings and Operation Mode

          64
      • 3.10.9.16 Switch S1D1 - 1/2

        65
        • Table 70. Switch S1D1 - 1/2: Descriptions

          65
        • Table 71. Switch S1D1 - 1/2: Settings and Operation Mode

          65
      • 3.10.9.17 Switch S4D1 - 1/2

        65
        • Table 72. Switch S4D1 - 1/2: Descriptions

          65
        • Table 73. Switch S4D1 - 1/2: Settings and Operation Mode

          65
      • 3.10.9.18 Switch S4D1 - 3/4

        65
        • Table 74. Switch S4D1 - 3/4: Descriptions

          65
        • Table 75. Switch S4D1 - 3/4: Settings and Operation Mode

          65
      • 3.10.9.19 Jumper J1G2

        66
        • Table 76. Jumper J1G2: Descriptions

          66
        • Table 77. Jumper J1G2: Settings and Operation Mode

          66
      • 3.10.9.20 Jumper J3E1

        66
        • Table 78. Jumper J3E1: Descriptions

          66
        • Table 79. Jumper J3E1: Settings and Operation Mode

          66
      • 3.10.9.21 Jumper J3G1

        66
        • Table 80. Jumper J3G1: Descriptions

          66
        • Table 81. Jumper J3G1: Settings and Operation Mode

          66
      • 3.10.9.22 Jumper J9E1

        67
        • Table 82. Jumper J9E1: Descriptions

          67
        • Table 83. Jumper J9E1: Settings and Operation Mode

          67
      • 3.10.9.23 Jumper J9F1

        67
        • Table 84. Jumper J9F1: Descriptions

          67
        • Table 85. Jumper J9F1: Settings and Operation Mode

          67
• External RAID Section 4

  69
  • 4.1 Private Device Configuration

    69
    • Table 86. Private Device Configuration Requirements

      69
    • Figure 17. IDSEL Routing for Private Device Configuration

      69
  • 4.2 Interrupt Routing

    70
    • Table 87. Interrupt Routing for Secondary PCI-X Private Device

      70
    • Figure 18. Interrupt Routing for Private Device Configuration

      70
• Software Reference 5

  71
  • 5.1 DRAM

    71
    • Table 88. DDR Memory Bias Voltage Minimum/Maximum Values

      71
  • 5.2 Components on the Peripheral Bus

    71
    • 5.2.1 Flash ROM

      72
      • Figure 19. Flash Connection to Peripheral Bus

        72
    • 5.2.2 UART

      73
      • Figure 20. UART Connection to Peripheral Bus

        73
      • Table 89. UART Register Settings

        73
    • 5.2.3 Rotary Switch

      73
    • 5.2.4 HEX Display

      74
      • Figure 21. Hex Display Connection to Peripheral Bus

        74
      • Figure 22. 7-Segment Display Bit Definition

        74
      • Figure 23. Register Bitmap: 7-Segment Display MSB FE84 0000h (Write Only)

        74
      • Figure 24. Register Bitmap: 7-Segment Display LSB FE85 0000h (Write Only)

        75
  • 5.3 Ethernet

    76
  • 5.4 Board Support Package (BSP) Examples

    77
    • 5.4.1 Intel® 80321 I/O Processor Memory Map

      77
      • Figure 25. Intel® 80321 I/O Processor Memory Map

        77
    • 5.4.2 Redboot* Intel® IQ80321 Memory Map

      78
    • 5.4.3 Redboot Intel® IQ80321 Physical Memory Map - Visual

      79
      • Figure 26. Redboot Intel® IQ80310 Physical Memory Map

        79
    • 5.4.4 Redboot Intel® IQ80321 Virtual Memory Map - Visual

      80
      • Figure 27. Redboot Intel® IQ80310 Virtual Memory Map

        80
    • 5.4.5 Redboot Intel® IQ80321 Files

      81
    • 5.4.6 Redboot Intel® IQ80321 DDR Memory Initialization Sequence

      82
    • 5.4.7 Redboot Switching

      83
• IQ80310 and IQ80321 Comparisons A

  85
  • Table 90. Intel® IQ80310 and Intel® IQ80321 Evaluation Platform Board Comparisons

    85
• Getting Started and Debugger B

  87
  • B.1 Introduction

    87
    • B.1.1 Purpose

      87
    • B.1.2 Necessary Hardware and Software

      87
    • B.1.3 Related Documents

      87
      • Table 91. Related Documents

        87
    • B.1.4 Related Web Sites

      88
  • B.2 Setup

    89
    • B.2.1 Hardware Setup

      89
      • Figure 28. Intel® IQ80321 Hardware Setup Flow Chart

        89
    • B.2.2 Software Setup

      90
      • Figure 29. Software Flow Diagram

        90
  • B.3 New Project Setup

    91
    • B.3.1 Creating a New Project

      91
    • B.3.2 Configuration

      92
  • B.4 Flashing with JTAG

    93
    • B.4.1 Overview

      93
    • B.4.2 Using Flash Programmer

      94
  • B.5 Debugging Out of Flash

    95
  • B.6 Building an Executable File From Example Code

    95
  • B.7 Running the Code|Lab Debugger

    96
    • B.7.1 Launching and Configuring Debugger

      96
    • B.7.2 Manually Loading and Executing an Application Program

      97
    • B.7.3 Displaying Source Code

      97
    • B.7.4 Using Breakpoints

      98
    • B.7.5 Stepping Through the Code

      99
    • B.7.6 Setting Code|Lab Debug Options

      99
  • B.8 Exploring the Code|Lab Debug Windows

    100
    • B.8.1 Toolbar Icons

      100
    • B.8.2 Workspace Window

      100
    • B.8.3 Source Code

      100
    • B.8.4 Debug and Console Windows

      100
    • B.8.5 Memory Window

      100
    • B.8.6 Registers Window

      101
    • B.8.7 Watch Window

      101
    • B.8.8 Variables Window

      101
  • B.9 Debugging Basics

    102
    • B.9.1 Overview

      102
    • B.9.2 Hardware and Software Breakpoints

      102
      • B.9.2.1 Software Breakpoints

        102
      • B.9.2.2 Hardware Breakpoints

        102
    • B.9.3 Exceptions/Trapping

      103
• Getting Started and Debugger C

  105
  • C.1 Introduction

    105
    • C.1.1 Purpose

      105
    • C.1.2 Necessary Hardware and Software

      105
    • C.1.3 Related Documents

      105
      • Table 92. Related Documents

        105
    • C.1.4 Related Web Sites

      106
  • C.2 Setup

    107
    • C.2.1 Hardware Setup

      107
      • Figure 30. Intel® IQ80321 Hardware Setup Flow Chart

        107
    • C.2.2 Software Setup

      108
      • Figure 31. Software Flow Diagram

        108
  • C.3 New Project Setup

    109
    • C.3.1 Creating a New Project

      109
    • C.3.2 Configuration

      110
  • C.4 Flashing with JTAG

    111
    • C.4.1 Overview

      111
    • C.4.2 Using Flash Programmer

      112
  • C.5 Debugging Out of Flash

    113
  • C.6 Building an Executable File From Example Code

    113
  • C.7 Running the Code|Lab Debugger

    114
    • C.7.1 Launching and Configuring Debugger

      114
    • C.7.2 Manually Loading and Executing an Application Program

      114
    • C.7.3 Displaying Source Code

      115
    • C.7.4 Using Breakpoints

      115
    • C.7.5 Stepping Through the Code

      116
    • C.7.6 Setting Code|Lab Debug Options

      116
  • C.8 Exploring the Code|Lab Debug Windows

    117
    • C.8.1 Toolbar Icons

      117
    • C.8.2 Workspace Window

      117
    • C.8.3 Source Code

      117
    • C.8.4 4 Debug and Console Windows

      117
    • C.8.5 Memory Window

      117
    • C.8.6 Registers Window

      118
    • C.8.7 Watch Window

      118
    • C.8.8 Variables Window

      118
  • C.9 Debugging Basics

    119
    • C.9.1 Overview

      119
    • C.9.2 Hardware and Software Breakpoints

      119
      • C.9.2.1 Software Breakpoints

        119
      • C.9.2.2 Hardware Breakpoints

        119
    • C.9.3 C.9.3 Exceptions/Trapping

      120