Benutzerhandbuch für Intel IXP1200

Inhaltsverzeichnis

• 1.0 Introduction

  7
  • 1.1 Purpose of ATM Example Design

    7
  • 1.2 Scope of Example Design

    7
    • 1.2.1 Supported / Not Implemented Functions

      8
  • 1.3 Background

    8
    • 1.3.1 Ethernet, IP and AAL5 Protocol Processing

      8
      • Figure 1. IP over ATM Encapsulation Format

        9
    • 1.3.2 Frame and PDU Length vs. IP Packet Length

      9
      • Figure 2. Frame and PDU Length vs. IP Packet Length

        10
    • 1.3.3 Expected Ethernet Transmit Bandwidth

      10
      • Figure 3. Expected Ethernet Transmit Bandwidth

        11
  • 1.4 Execution Environment

    11
    • 1.4.1 Software

      11
      • Figure 4. Developer’s Workbench - ATM Data Stream Dialog Box

        12
      • Figure 5. Developer’s Workbench - IX Bus Device Status Window

        13
    • 1.4.2 Hardware

      13
• 2.0 System Overview

  13
  • 2.1 System Programming Model

    13
    • Figure 6. System Programming Model

      14
  • 2.2 StrongARM Core Software

    14
  • 2.3 Software Partitioning

    15
    • Figure 7. IXP1240 1xATM OC-12 and 8xEthernet 100Mbps Microengine Partitioning

      15
    • Figure 8. IXP1240 OC-3 4xATM and 8xEthernet 100Mbps Microengine Partitioning

      16
    • 2.3.1 Lookup Tables

      16
      • Figure 9. IXP1200 2xATM OC-3 Software-CRC and 4xEthernet 100Mbps Microengine Partitioning

        17
  • 2.4 Data Flow

    17
    • 2.4.1 ATM to Ethernet Data Flow

      17
      • 2.4.1.1 VC Lookup

        17
      • 2.4.1.2 IP Lookup Table

        18
        • Figure 10. ATM to Ethernet Processing Steps

          18
    • 2.4.2 Ethernet to ATM Data Flow

      19
      • Figure 11. Ethernet to ATM Processing Steps

        19
  • 2.5 StrongARM Core Initialization

    19
  • 2.6 Microengine Initialization

    20
• 3.0 Microengine Functional Blocks

  20
  • 3.1 ATM Receive Microengine

    20
    • 3.1.1 Structure

      20
    • 3.1.2 High Level Algorithm

      21
      • Figure 12. ATM Receive High Level Algorithm

        21
  • 3.2 ATM Transmit Microengine

    22
    • 3.2.1 High Level Algorithm

      22
      • Figure 13. ATM Transmit High Level Algorithm

        22
  • 3.3 IP-Router Microengine

    23
    • 3.3.1 Structure

      23
    • 3.3.2 High Level Algorithm

      23
      • Figure 14. IP Router High Level Algorithm

        23
  • 3.4 Ethernet Receive Microengine

    23
    • 3.4.1 Ethernet Receive Structure

      24
    • 3.4.2 Ethernet Receive High Level Algorithm

      24
      • Figure 15. Ethernet Receive High Level Algorithm

        24
  • 3.5 Ethernet Transmit Microengine

    24
    • 3.5.1 Ethernet Transmit Structure

      25
    • 3.5.2 High Level Algorithm

      25
  • 3.6 CRC-32 Calculations using IXP1240/1250 Hardware

    25
    • 3.6.1 CRC-32 Hardware Checking on Receive

      25
      • Figure 16. First Cell of a PDU in RFIFO and in DRAM

        26
      • Figure 17. Two-Cell PDU in DRAM

        26
    • 3.6.2 CRC-32 Hardware Generation on Transmit

      27
      • Figure 18. Transmit cell as seen in DRAM

        27
      • Figure 19. Transmit cell seen in TFIFO

        27
      • 3.6.2.1 Transmit Alignment

        27
  • 3.7 CRC-32 Checker and Generator Microengines (Soft-CRC)

    28
    • 3.7.1 Functional Differences between Checker and Generator

      28
    • 3.7.2 CRC-32 Checker and Generator High Level Algorithm

      29
      • Figure 20. CRC-32 High Level Algorithm

        29
    • 3.7.3 CRC-32 Computation

      29
• 4.0 Software Subsystems & Data Structures

  29
  • 4.1 Virtual Circuit Lookup Table - atm_vc_table.uc

    29
    • 4.1.1 VC Table Function

      29
    • 4.1.2 VC_TABLE_HASHED Structure

      30
      • Figure 21. Hashed VC Table Structure

        31
    • 4.1.3 VC_TABLE_LINEAR Structure

      31
      • Figure 22. VC Table Index

        32
    • 4.1.4 VC Table Management API - atm_utils.c

      32
    • 4.1.5 VC Table Entry

      32
      • Figure 23. VC Lookup Entry Table (VC_TABLE_HASHED)

        32
      • Figure 24. VC Lookup Table Entry (VC_TABLE_LINEAR)

        33
  • 4.2 Virtual Circuit Lookup Table Cache

    34
    • 4.2.1 VC Cache Function

      34
      • 4.2.1.1 OC-12 Configuration

        34
      • 4.2.1.2 OC-3 Configuration

        34
    • 4.2.2 VC Cache Structure

      34
    • 4.2.3 VC Cache API

      35
  • 4.3 IP Lookup Table

    35
    • 4.3.1 IP Table Function

      35
    • 4.3.2 IP Table Structure

      35
    • 4.3.3 IP Table Management API

      36
      • 4.3.3.1 route_table_init()

        36
      • 4.3.3.2 mtu_change()

        36
      • 4.3.3.3 atm_route_add()

        36
      • 4.3.3.4 enet_route_add()

        37
      • 4.3.3.5 rt_ent_info()

        37
      • 4.3.3.6 route_delete()

        37
      • 4.3.3.7 rt_help ()

        37
    • 4.3.4 IP Route Table Entry

      37
      • Figure 25. IP Route Table Entry - ATM Destination

        38
      • Figure 26. IP Route Table Entry - Ethernet Destination

        38
  • 4.4 SRAM Buffer Descriptors and DRAM Data Buffers

    38
    • Figure 27. SRAM Descriptor to DRAM Buffer Mapping

      39
    • 4.4.1 SRAM Buffer Descriptor Format

      39
      • Figure 28. Buffer Descriptor Format for ATM Transmit Destination Port

        39
      • Figure 29. Buffer Descriptor Format for Ethernet Transmit Destination Port

        40
    • 4.4.2 DRAM Data Buffer Format

      40
      • Figure 30. DRAM Data Buffer Format - 12 Byte Offset (Received by ATM)

        40
      • Figure 31. DRAM Data Buffer Format - 6 Byte Offset (Received by ATM, Transmitted by Ethernet)

        40
      • Figure 32. DRAM Data Buffer Format - 6 Byte Offset (Received by Ethernet, Transmitted by ATM)

        40
      • Figure 33. DRAM Data Buffer Received by Ethernet

        40
    • 4.4.3 System Limit on Packet Buffers

      41
  • 4.5 Sequence Numbers - sequence.uc

    41
    • 4.5.1 SEQUENCE_HANDLE Usage

      41
    • 4.5.2 Usage Model

      42
      • 4.5.2.1 Example

        42
  • 4.6 Message Queues - msgq.uc

    42
    • 4.6.1 MSGQ_HANDLE Parameters

      43
    • 4.6.2 msgq_init_queue()

      43
    • 4.6.3 msgq_init_regs()

      43
    • 4.6.4 msgq_send()

      43
    • 4.6.5 msgq_receive()

      44
    • 4.6.6 Example

      44
  • 4.7 Buffer Descriptor Queues - bdq.uc

    45
    • 4.7.1 BDQ Management Macros

      45
      • 4.7.1.1 Features

        45
      • 4.7.1.2 Limitations

        45
        • Figure 34. Buffer Descriptor Queue API

          46
        • Figure 35. Buffer Descriptor Queue Descriptor Structure (Resides in SRAM)

          46
        • Figure 36. Buffer Descriptor Queue Structure (Only Relevant Part Shown)

          46
  • 4.8 Counters

    46
    • 4.8.1 Global Parameters

      47
    • 4.8.2 Use of the Counter Subsystem

      47
      • 4.8.2.1 Counter Base Address

        47
      • 4.8.2.2 Counter Index

        47
      • 4.8.2.3 Global Counter Enable and Flags

        48
    • 4.8.3 counters.uc

      49
      • 4.8.3.1 counter_reset()

        49
      • 4.8.3.2 counter_inc()

        49
      • 4.8.3.3 port_counter_inc()

        49
    • 4.8.4 counters.c

      51
      • 4.8.4.1 counters_init()

        51
      • 4.8.4.2 counters_print()

        51
  • 4.9 Global $transfer Register Name Manager - xfer.uc

    52
  • 4.10 Mutex Vectors

    53
    • 4.10.1 mutex_vector_init()

      53
    • 4.10.2 mutex_vector_enter()

      53
    • 4.10.3 mutex_vector_exit()

      53
  • 4.11 Inter-Thread Signalling

    54
• 5.0 Project Configuration / Modifying the Example Design

  54
  • 5.1 project_config.h

    54
  • 5.2 system_config.h

    55
  • 5.3 Switching Between Hardware Configurations

    55
• 6.0 Testing Environments

  55
• 7.0 Simulation Support (Scripts, etc.)

  56
• 8.0 Limitations

  56
• 9.0 Extending the Example Design

  56
• 10.0 Document Conventions

  57
  • Figure 37. Illustration of Array of 32-bit Words

    57
  • Figure 38. Illustration of Byte Sequence

    57
• 11.0 Acronyms & Definitions

  57
  • Figure 39. Definitions

    57
• 12.0 Related Documents

  58
  • IXP1200 Network Processor Family

    1