Benutzerhandbuch für Intel N2820

Intel

Produktcode

FH8065301616603

Datenbogen (English)

Datenbogen (FH8065301616603)

Inhaltsverzeichnis

1 Introduction
15
- 1.1 Terminology
  17
- 1.2 Feature Overview
  18
2 Physical Interfaces
23
- 2.1 Pin States Through Reset
  25
- 2.2 System Memory Controller Interface Signals
  26
- 2.3 PCI Express* 2.0 Interface Signals
  27
- 2.4 USB 2.0 Host (EHCI/xHCI) Interface Signals
  27
- 2.5 USB 2.0 HSIC Interface Signals
  28
- 2.6 USB 3.0 (xHCI) Host Interface Signals
  28
- 2.7 Serial ATA (SATA) 2.0 Interface Signals
  28
- 2.8 Integrated Clock Interface Signals
  29
- 2.9 Display – Digital Display Interface (DDI) Signals
  30
- 2.10 Display – VGA Interface Signals
  31
- 2.11 Intel® High Definition Audio Interface Signals
  31
- 2.12 SPCU – iLB – Real Time Clock (RTC) Interface Signals
  32
- 2.13 PCU – iLB – Low Pin Count (LPC) Bridge Interface Signals
  32
- 2.14 PCU – Serial Peripheral Interface (SPI) Signals
  33
- 2.15 PCU – System Management Bus (SMBus) Interface Signals
  33
- 2.16 PCU – Power Management Controller (PMC) Interface Signals
  34
- 2.17 JTAG and Debug Interface Signals
  34
- 2.18 Miscellaneous Signals
  35
- 2.19 GPIO Signals
  35
- 2.20 Power And Ground Pins
  40
- 2.21 Hardware Straps
  42
- 2.22 Configurable IO – GPIO Multiplexing
  42
3 Register Access Methods
43
- 3.1 Fixed IO Register Access
  43
- 3.2 Fixed Memory Mapped Register Access
  43
- 3.3 IO Referenced Register Access
  43
- 3.4 Memory Referenced Register Access
  44
- 3.5 PCI Configuration Register Access
  44
- 3.6 Message Bus Register Access
  46
- 3.7 Register Field Access Types
  47
4 Mapping Address Spaces
49
- 4.1 Physical Address Space Mappings
  49
- 4.2 IO Address Space
  54
- 4.3 PCI Configuration Space
  56
5 Integrated Clock
58
- 5.1 Features
  59
6 Power Management
61
- 6.1 Power Management Features
  61
- 6.2 Power Management States Supported
  61
- 6.3 Processor Core Power Management
  65
- 6.4 Memory Controller Power Management
  71
- 6.5 PCI Express* (PCIe*) Power Management
  73
7 Thermal Management
74
- 7.1 Overview
  74
- 7.2 Thermal Design Power (TDP)
  74
- 7.3 Scenario Design Power (SDP)
  75
- 7.4 Thermal Sensors
  75
- 7.5 Hardware Trips
  76
- 7.6 Processor Programmable Trips
  76
- 7.7 Platform Trips
  77
- 7.8 Thermal Throttling Mechanisms
  77
- 7.9 Thermal Status
  77
8 Electrical Specifications
78
- 8.1 Thermal Specifications
  78
- 8.2 Storage Conditions
  79
- 8.3 Voltage and Current Specifications
  80
- 8.4 Crystal Specifications
  90
- 8.5 DC Specifications
  91
9 Package Information
107
- 9.1 Processor Attributes
  107
- 9.2 Package Diagrams
  108
10 Processor Core
109
- 10.1 Features
  109
- 10.2 Platform Identification and CPUID
  112
- 10.3 References
  112
- 10.4 System Memory Controller
  113
- 10.5 Signal Descriptions
  113
- 10.6 Features
  115
11 Processor Transaction Router
118
- 11.1 Transaction Router C-Unit PCI Configuration Registers
  119
12 Graphics, Video, and Display
123
- 12.1 Features
  123
- 12.2 Processor Graphics Display
  124
- 12.3 Display Pipes
  125
- 12.4 Display Physical Interfaces
  125
- 12.5 References
  131
- 12.6 3D Graphics and Video
  131
- 12.7 Features
  132
- 12.8 VED (Video Encode/Decode)
  134
13 Serial ATA (SATA)
135
- 13.1 Signal Descriptions
  135
- 13.2 Features
  136
- 13.3 References
  138
- 13.4 Register Map
  139
- 13.5 SATA PCI Configuration Registers
  140
- 13.6 SATA Legacy IO Registers
  172
- 13.7 SATA Index Pair IO Registers
  178
- 13.8 SATA AHCI Memory Mapped IO Registers
  180
- 13.9 SATA Primary Read Command IO Registers
  219
- 13.10 SATA Primary Write Command IO Registers
  224
- 13.11 SATA Primary Read Control IO Registers
  226
- 13.12 SATA Primary Write Control IO Registers
  227
- 13.13 SATA Secondary Read Command IO Registers
  228
- 13.14 SATA Secondary Write Command IO Registers
  233
- 13.15 SATA Secondary Read Control IO Registers
  235
- 13.16 SATA Secondary Write Control IO Registers
  236
- 13.17 SATA Lane 0 Electrical Register Address Map
  237
- 13.18 SATA Lane 0 Electrical Register Address Map
  270
- 13.19 SATA Lane 1 Electrical Register Address Map
  287
- 13.20 SATA Lane 1 Electrical Register Address Map
  321
14 USB Host Controller Interfaces (xHCI, EHCI)
338
- 14.1 Signal Descriptions
  338
- 14.2 USB 3.0 xHCI (Extensible Host Controller Interface)
  340
- 14.3 USB 2.0 Enhanced Host Controller Interface (EHCI)
  341
- 14.4 References
  342
- 14.5 Register Map
  343
- 14.6 USB xHCI PCI Configuration Registers
  344
- 14.7 USB xHCI Memory Mapped I/O Registers
  380
15 Intel® High Definition Audio (Intel® HD Audio)
538
- 15.1 Signal Descriptions
  539
- 15.2 Features
  540
- 15.3 References
  540
- 15.4 Register Map
  541
- 15.5 HD Audio PCI Configuration Registers
  542
- 15.6 HD Audio Memory Mapped I/O Registers
  575
16 Low Power Engine (LPE) for Audio (I2S)
697
- 16.1 Signal Descriptions
  697
- 16.2 Features
  698
- 16.3 Detailed Block Level Description
  700
- 16.4 Software Implementation Considerations
  702
- 16.5 Clocks
  704
- 16.6 SSP (I2S)
  707
- 16.7 Programming Model
  713
- 16.8 Register Map
  717
17 Intel® Trusted Execution Engine (Intel® TXE)
718
- 17.1 Features
  718
18 PCI Express* 2.0
720
- 18.1 Signal Descriptions
  720
- 18.2 Features
  721
- 18.3 References
  724
- 18.4 Register Map
  724
- 18.5 PCI Configuration Registers
  725
- 18.6 PCI Express* PCI Configuration Registers
  726
- 18.7 PCI Express* Lane 0 Electrical Address Map
  773
- 18.8 PCI Express* Lane 0 Electrical Address Map
  805
- 18.9 PCI Express* Lane 1 Electrical Address Map
  822
- 18.10 PCI Express* Lane 1 Electrical Address Map
  853
- 18.11 PCI Express* Lane 2 Electrical Address Map
  870
- 18.12 PCI Express* Lane 2 Electrical Address Map
  901
- 18.13 PCI Express* Lane 3 Electrical Address Map
  918
- 18.14 PCI Express* Lane 3 Electrical Address Map
  949
19 Platform Controller Unit (PCU) Overview
966
- 19.1 Features
  966
- 19.2 PCU iLB LPC Port 80h I/O Registers
  969
20 PCU – Power Management Controller (PMC)
978
- 20.1 Signal Descriptions
  978
- 20.2 Features
  980
- 20.3 USB Per-Port Register Write Control
  987
- 20.4 References
  988
- 20.5 PCU PMC Memory Mapped I/O Registers
  989
- 20.6 PCU PMC IO Registers
  1023
- 20.7 PCU iLB PMC I/O Registers
  1026
21 PCU – Serial Peripheral Interface (SPI)
1044
- 21.1 Signal Descriptions
  1044
- 21.2 Features
  1045
- 21.3 Use
  1058
- 21.4 PCU SPI for Firmware Memory Mapped I/O Registers
  1060
22 PCU – Universal Asynchronous Receiver/Transmitter (UART)
1096
- 22.1 Signal Descriptions
  1096
- 22.2 Features
  1097
- 22.3 Use
  1099
- 22.4 UART Enable/Disable
  1099
- 22.5 Register Map
  1100
- 22.6 IO Mapped Registers
  1100
- 22.7 PCU iLB UART IO Registers
  1101
23 PCU – System Management Bus (SMBus)
1110
- 23.1 Signal Descriptions
  1110
- 23.2 Features
  1111
- 23.3 Use
  1117
- 23.4 References
  1118
- 23.5 Register Map
  1118
- 23.6 PCU SMBus PCI Configuration Registers
  1120
- 23.7 PCU SMBus Memory Mapped I/O Registers
  1135
- 23.8 PCU SMBus I/O Registers
  1146
24 PCU – Intel® Legacy Block (iLB) Overview
1159
- 24.1 Signal Descriptions
  1159
- 24.2 Features
  1160
- 24.3 PCU iLB Interrupt Decode and Route
  1162
25 PCU – iLB – Low Pin Count (LPC) Bridge
1201
- 25.1 Signal Descriptions
  1201
- 25.2 Features
  1202
- 25.3 Use
  1207
- 25.4 References
  1208
- 25.5 Register Map
  1208
- 25.6 PCU iLB Low Pin Count (LPC) Bridge PCI Configuration Registers
  1210
- 25.7 PCU iLB LPC BIOS Control Memory Mapped I/O Registers
  1230
26 PCU – iLB – Real Time Clock (RTC)
1231
- 26.1 Signal Descriptions
  1231
- 26.2 Features
  1232
- 26.3 Interrupts
  1233
- 26.4 References
  1234
- 26.5 Register Map
  1234
- 26.6 IO Mapped Registers
  1235
- 26.7 Indexed Registers
  1235
- 26.8 PCU iLB Real Time Clock (RTC) I/O Registers
  1237
27 PCU – iLB – 8254 Timers
1239
- 27.1 Signal Descriptions
  1239
- 27.2 Features
  1239
- 27.3 Use
  1240
- 27.4 Register Map
  1243
- 27.5 IO Mapped Registers
  1243
- 27.6 PCU iLB 8254 Timers IO Registers
  1244
28 PCU – iLB – High Precision Event Timer (HPET)
1250
- 28.1 Features
  1250
- 28.2 References
  1252
- 28.3 Register Map
  1252
- 28.4 Memory Mapped Registers
  1252
- 28.5 PCU iLB High Performance Event Timer (HPET) Memory Mapped IO Registers
  1253
29 PCU – iLB – GPIO
1262
- 29.1 Signal Descriptions
  1262
- 29.2 Features
  1262
- 29.3 Use
  1263
- 29.4 Register Map
  1264
- 29.5 GPIO Registers
  1264
30 PCU – iLB – Interrupt Decoding and Routing
1266
- 30.1 Features
  1266
31 PCU – iLB – IO APIC
1268
- 31.1 Features
  1268
- 31.2 Use
  1270
- 31.3 References
  1270
- 31.4 Indirect I/O APIC Registers
  1271
- 31.5 PCU iLB IO APIC Memory Mapped I/O Registers
  1272
32 PCU – iLB – 8259 Programmable Interrupt Controllers (PIC)
1274
- 32.1 Features
  1274
- 32.2 IO Mapped Registers
  1281
- 32.3 PCU iLB 8259 Interrupt Controller (PIC) I/O Registers
  1283

Datenbogen (FH8065301616603)

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7,4 MB
Seiten:

1294
Language:

English

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