BenutzerhandbuchInhaltsverzeichnisIntroduction 1151.1 Scope151.2 Overview151.3 Ethernet Controller Features161.3.1 PCI Features161.3.2 CSA Features (82547GI/EI Only)161.3.3 Network Side Features161.3.4 Host Offloading Features171.3.5 Additional Performance Features181.3.6 Manageability Features (Not Applicable to the 82544GC/EI or 82541ER)191.3.7 Additional Ethernet Controller Features191.3.8 Technology Features191.4 Conventions201.4.1 Register and Bit References201.4.2 Byte and Bit Designations201.5 Related Documents201.6 Memory Alignment Terminology20Architectural Overview 2212.1 Introduction212.2 External Architecture222.3 Microarchitecture242.3.1 PCI/PCI-X Core Interface242.3.2 82547GI/EI CSA Interface252.3.3 DMA Engine and Data FIFO252.3.4 10/100/1000 Mb/s Receive and Transmit MAC Blocks262.3.5 MII/GMII/TBI/Internal SerDes Interface Block262.3.6 10/100/1000 Ethernet Transceiver (PHY)272.3.7 EEPROM Interface272.3.8 FLASH Memory Interface282.4 DMA Addressing282.5 Ethernet Addressing292.6 Interrupts302.7 Hardware Acceleration Capability312.7.1 Checksum Offloading312.7.2 TCP Segmentation312.8 Buffer and Descriptor Structure31Receive and Transmit Description 3333.1 Introduction333.2 Packet Reception333.2.1 Packet Address Filtering333.2.2 Receive Data Storage343.2.3 Receive Descriptor Format343.2.3.1 Receive Descriptor Status Field353.2.3.2 Receive Descriptor Errors Field363.2.3.3 Receive Descriptor Special Field383.2.4 Receive Descriptor Fetching393.2.5 Receive Descriptor Write-Back403.2.5.1 Receive Descriptor Packing403.2.5.2 Null Descriptor Padding403.2.6 Receive Descriptor Queue Structure403.2.7 Receive Interrupts423.2.7.1 Receive Timer Interrupt423.2.7.2 Small Receive Packet Detect443.2.7.3 Receive Descriptor Minimum Threshold (ICR.RXDMT)453.2.7.4 Receiver FIFO Overrun453.2.8 82544GC/EI Receive Interrupts453.2.9 Receive Packet Checksum Offloading453.2.9.1 MAC Address Filter473.2.9.2 SNAP/VLAN Filter483.2.9.3 IPv4 Filter483.2.9.4 IPv6 Filter483.2.9.5 UDP/TCP Filter483.3 Packet Transmission483.3.1 Transmit Data Storage493.3.2 Transmit Descriptors493.3.3 Legacy Transmit Descriptor Format503.3.3.1 Transmit Descriptor Command Field Format523.3.3.2 Transmit Descriptor Status Field Format533.3.4 Transmit Descriptor Special Field Format543.3.5 TCP/IP Context Transmit Descriptor Format553.3.6 TCP/IP Context Descriptor Layout563.3.6.1 TCP/UDP Offload Transmit Descriptor Command Field583.3.6.2 TCP/UDP Offload Transmit Descriptor Status Field603.3.7 TCP/IP Data Descriptor Format603.3.7.1 TCP/IP Data Descriptor Command Field623.3.7.2 TCP/IP Data Descriptor Status Field633.3.7.3 TCP/IP Data Descriptor Option Field643.3.7.4 TCP/IP Data Descriptor Special Field643.4 Transmit Descriptor Ring Structure653.4.1 Transmit Descriptor Fetching673.4.2 Transmit Descriptor Write-back673.4.3 Transmit Interrupts683.4.3.1 Delayed Transmit Interrupts693.5 TCP Segmentation693.5.1 Assumptions703.5.2 Transmission Process703.5.2.1 TCP Segmentation Data Fetch Control713.5.3 TCP Segmentation Performance713.5.4 Packet Format713.5.5 TCP Segmentation Indication723.5.6 TCP Segmentation Use of Multiple Data Descriptors733.5.7 IP and TCP/UDP Headers743.5.8 Transmit Checksum Offloading with TCP Segmentation783.5.9 IP/TCP/UDP Header Updating793.5.9.1 TCP/IP/UDP Header for the First Frame813.5.9.2 TCP/IP/UDP Header for the Subsequent Frames813.5.9.3 TCP/IP/UDP Header for the Last Frame823.6 IP/TCP/UDP Transmit Checksum Offloading82PCI Local Bus Interface 4854.1 PCI Configuration854.1.1 PCI-X Configuration Registers934.1.1.1 PCI-X Capability ID934.1.1.2 Next Capability934.1.1.3 PCI-X Command944.1.1.4 PCI-X Status954.1.2 Reserved and Undefined Addresses964.1.3 Message Signaled Interrupts974.1.3.1 Message Signaled Interrupt Configuration Registers974.2 Commands994.3 PCI/PCI-X Command Usage1014.3.1 Memory Write Operations1014.3.1.1 MWI Bursts1024.3.1.2 MW Bursts1034.3.2 Memory Read Operations1034.3.2.1 PCI-X Command Usage1034.4 Cache Line Information1044.4.1 Target Transaction Termination1054.5 Interrupt Assignment (82547GI/EI Only)1054.6 LAN Disable1054.7 CardBus Application (82541PI/GI/EI Only)106EEPROM Interface 51075.1 General Overview1075.2 Component Identification Via Programming Interface1085.3 EEPROM Device and Interface1095.3.1 Software Access1105.4 Signature and CRC Fields1105.5 EEUPDATE Utility1115.5.1 Command Line Parameters1115.6 EEPROM Address Map1125.6.1 Ethernet Address (Words 00h-02h)1175.6.2 Software Compatibility Word (Word 03h)1175.6.3 SerDes Configuration (Word 04h)1185.6.4 EEPROM Image Version (Word 05h)1185.6.5 Compatibility Fields (Word 05h - 07h)1185.6.6 PBA Number (Word 08h, 09h)1185.6.7 Initialization Control Word 1 (Word 0Ah)1195.6.8 Subsystem ID (Word 0Bh)1205.6.9 Subsystem Vendor ID (Word 0Ch)1205.6.10 Device ID (Word 0Dh, 11h)1215.6.11 Vendor ID (Word 0Eh)1215.6.12 Initialization Control Word 2 (Word 0Fh)1215.6.13 PHY Register Address Data (Words 10h, 11h, and 13h - 1Eh)1235.6.14 OEM Reserved Words (Words 10h, 11h, 13h - 1Fh)1235.6.15 EEPROM Size (Word 12h)1235.6.16 Common Power (Word 12h)1235.6.17 Software Defined Pins Control (Word 10h, 20h)1235.6.18 CSA Port Configuration 2 (Word 21h)1255.6.19 Circuit Control (Word 21h)1265.6.20 D0 Power (Word 22h high byte)1265.6.21 D3 Power (Word 22h low byte)1265.6.22 Reserved Words (23h - 2Eh)1265.6.23 Reserved Words (23h - 2Fh)1265.6.24 Management Control (Word 13h, 23h)1275.6.25 SMBus Slave Address (Word 14h low byte, 24h low byte)1285.6.26 Initialization Control 3 (Word 14h high byte, 24h high byte)1295.6.27 IPv4 Address (Words 15h - 16h and 25h - 26h)1305.6.28 IPv6 Address (words 17h - 1Eh1 and 27h - 2Eh)1305.6.29 LED Configuration Defaults (Word 2Fh)1305.6.30 Boot Agent Main Setup Options (Word 30h)1305.6.31 Boot Agent Configuration Customization Options (Word 31h)1325.6.32 Boot Agent Configuration Customization Options (Word 32h)1345.6.33 IBA Capabilities (Word 33h)1355.6.34 IBA Secondary Port Configuration (Words 34h-35h)1355.6.35 Checksum Word Calculation (Word 3Fh)1365.6.36 82546GB/EB Dual-Channel Fiber Wake on LAN (WOL) Mode and Functionality (Word 0Ah, 20h)1365.6.37 EEPROM Images1365.7 Parallel FLASH Memory137FLASH Memory Interface 71397.1 FLASH Interface Operation1397.2 FLASH Control and Accesses1397.2.1 Read Accesses1407.2.2 Write Accesses140Power Management 61436.1 Introduction to Power Management1436.2 Assumptions1436.3 D3cold support1446.3.1 Power States1446.3.1.1 Dr State1456.3.1.2 D0u State1456.3.1.3 D0a (D0 active)1466.3.1.4 D31466.3.2 Timing1466.3.2.1 Power Up (Off to Dr to D0u to D0a)1476.3.2.2 Transition From D0a to D3 and Back Without PCI Reset1486.3.2.3 Transition From D0a to D3 and Back with PCI Reset1496.3.2.4 PCI Reset Without Transition to D31506.3.3 PCI Power Management Registers1516.3.3.1 Capability ID 1 Byte Offset = 0 (RO)1516.3.3.2 Next Item Pointer 1 Byte Offset = 1 (RO)1516.3.3.3 Power Management Capabilities - (PMC) 2 Bytes Offset = 2 (RO)1526.3.3.4 Power Management Control / Status Register - (PMCSR) 2 Bytes Offset = 4 (RO)1536.3.3.5 PMCSR_BSE Bridge Support Extensions 1 Byte Offset = 6 (RO)1546.3.3.6 Data Register 1 Byte Offset = 7 (RO)1546.4 Wakeup1556.4.1 Advanced Power Management Wakeup1556.4.2 ACPI Power Management Wakeup1566.4.3 Wakeup Packets1576.4.3.1 Pre-Defined Filters1576.4.3.2 Directed IPv6 Packet1626.4.3.3 Flexible Filter1636.4.3.4 IPv6 Neighbor Discovery Filter1646.4.3.5 Wakeup Packet Storage165Ethernet Interface 81678.1 Introduction1678.2 Link Interfaces Overview1678.2.1 Internal SerDes Interface/TBI Mode- 1Gb/s1688.2.1.1 Gigabit Physical Coding Sub-Layer (PCS) for the Internal SerDes1688.2.1.2 8B10B Encoding/Decoding1688.2.1.3 Code Groups and Ordered Sets1698.2.2 GMII - 1 Gb/s1698.2.3 MII - 10/100 Mb/s1708.3 Internal Interface1708.4 Duplex Operation1708.4.1 Full Duplex1718.4.2 Half Duplex1718.4.2.1 Carrier Extension (1000 Mb/s Only)1728.4.2.2 Packet Bursting1728.5 Auto-Negotiation and Link Setup1738.6 Auto-Negotiation and Link Setup1738.6.1 Link Configuration in Internal Serdes/TBI Mode1748.6.1.1 Link Speed1748.6.1.2 Auto-Negotiation1748.6.1.3 Hardware Auto-Negotiation1758.6.1.4 Software Auto-Negotiation1768.6.1.5 Forcing Link1778.6.2 Internal GMII/MII Mode1778.6.2.1 Auto-Negotiation1778.6.2.2 Link Speed1788.6.2.3 Duplex1798.6.2.4 MII Management Registers1798.6.2.5 Comments Regarding Forcing Link1798.6.3 Internal SerDes Mode Control Bit Resolution1808.6.4 Internal PHY Mode Control Bit Resolution1818.6.5 Loss of Signal/Link Status Indication1838.6.5.1 Internal Serdes Mode1838.6.5.2 Internal PHY Mode1838.7 10/100 Mb/s Specific Performance Enhancements1848.7.1 Adaptive IFS1848.7.2 Flow Control1858.7.3 MAC Control Frames & Reception of Flow Control Packets1858.7.4 Discard PAUSE Frames and Pass MAC Control Frames1878.7.5 Transmission of PAUSE Frames1878.7.6 Software Initiated PAUSE Frame Transmission1888.7.7 External Control of Flow Control Operation188802.1q VLAN Support 91899.1 802.1q VLAN Packet Format1899.1.1 802.1q Tagged Frames1899.2 Transmitting and Receiving 802.1q Packets1909.2.1 Adding 802.1q Tags on Transmits1909.2.2 Stripping 802.1q Tags on Receives1909.3 802.1q VLAN Packet Filtering190Configurable LED Outputs 1019310.1 Configurable LED Outputs19310.1.1 Selecting an LED Output Source19310.1.2 Polarity Inversion19410.1.3 Blink Control194PHY Functionality and Features 1119711.1 Auto-Negotiation19711.1.1 Overview19711.1.2 Next Page Exchanges19811.1.3 Register Update19811.1.4 Status19911.2 MDI/MDI-X Crossover (copper only)19911.2.1 Polarity Correction (copper only)20011.2.2 10/100 Downshift (82540EP/EM Only)20011.3 Cable Length Detection (copper only)20111.4 PHY Power Management (copper only)20111.4.1 Link Down - Energy Detect (copper only)20111.4.2 D3 State, No Link Required (copper only)20211.4.3 D3 Link-Up, Speed-Management Enabled (copper only)20211.4.4 D3 Link-Up, Speed-Management Disabled (copper only)20211.5 Initialization20311.5.1 MDIO Control Mode20311.6 Determining Link State20411.6.1 False Link20511.6.2 Forced Operation20511.6.3 Auto Negotiation20611.6.4 Parallel Detection20611.7 Link Criteria20611.7.1 1000BASE-T20611.7.2 100BASE-TX20611.7.3 10BASE-T20711.8 Link Enhancements20711.8.1 SmartSpeed20711.8.1.1 Using SmartSpeed20711.8.2 Flow Control20711.9 Management Data Interface20811.10 Low Power Operation20811.10.1 Powerdown via the PHY Register20911.10.2 Smart Power-Down20911.11 1000 Mbps Operation20911.11.1 Introduction20911.11.2 Transmit Functions21111.11.2.1 Scrambler21111.11.3 Transmit FIFO21111.11.3.1 Transmit Phase-Locked Loop PLL21111.11.3.2 Trellis Encoder21111.11.3.3 4DPAM5 Encoder21111.11.3.4 Spectral Shaper21211.11.3.5 Low-Pass Filter21211.11.3.6 Line Driver21211.11.3.7 Transmit/Receive Flow21211.11.4 Receive Functions21311.11.4.1 Hybrid21311.11.4.2 Automatic Gain Control21311.11.4.3 Timing Recovery21311.11.4.4 Analog-to-Digital Converter21311.11.4.5 Digital Signal Processor21311.11.4.6 Descrambler21411.11.4.7 Viterbi Decoder/Decision Feedback Equalizer (DFE)21411.11.4.8 4DPAM5 Decoder21411.12 100 Mbps Operation21411.13 10 Mbps Operation21411.13.1 Link Test21511.13.2 10Base-T Link Failure Criteria and Override21511.13.3 Jabber21511.13.4 Polarity Correction21511.13.5 Dribble Bits21511.14 PHY Line Length Indication215Dual Port Characteristics 1221712.1 Introduction21712.2 Features of Each MAC21712.2.1 PCI/PCI-X interface21712.2.2 MAC Configuration Register Space21912.2.3 SDP, LED, INT# output21912.3 Shared EEPROM22012.3.1 EEPROM Map22012.3.2 EEPROM Arbitration22012.4 Shared FLASH22112.4.1 FLASH Access Contention22112.5 LAN Disable22212.5.1 Overview22212.5.2 Values Sampled on Reset22212.5.3 Multi-Function Advertisement22312.5.4 Interrupt Use22312.5.5 Power Reporting22312.5.6 Summary224Register Descriptions 1322513.1 Introduction22513.2 Register Conventions22513.2.1 Memory and I/O Address Decoding22613.2.1.1 Memory-Mapped Access to Internal Registers and Memories22613.2.1.2 Memory-Mapped Access to FLASH22613.2.1.3 Memory-Mapped Access to Expansion ROM22613.2.2 I/O-Mapped Internal Register, Internal Memory, and Flash22713.2.2.1 IOADDR22713.2.2.2 IODATA22713.3 PCI-X Register Access Split23313.4 Main Register Descriptions23413.4.1 Device Control Register23413.4.2 Device Status Register23913.4.3 EEPROM/Flash Control & Data Register24213.4.4 EEPROM Read Register24413.4.5 Flash Access24613.4.6 Extended Device Control Register24713.4.7 MDI Control Register25213.4.7.1 PHY Registers25413.4.8 Flow Control Address Low29313.4.9 Flow Control Address High29313.4.10 Flow Control Type29413.4.11 VLAN Ether Type29413.4.12 Flow Control Transmit Timer Value29513.4.13 Transmit Configuration Word Register29613.4.14 Receive Configuration Word Register29713.4.15 LED Control29913.4.15.1 MODE Encodings for LED Outputs130013.4.16 Packet Buffer Allocation30213.4.17 Interrupt Cause Read Register30313.4.18 Interrupt Throttling Register30513.4.19 Interrupt Cause Set Register30613.4.20 Interrupt Mask Set/Read Register30713.4.21 Interrupt Mask Clear Register30813.4.22 Receive Control Register31013.4.23 Flow Control Receive Threshold Low31413.4.24 Flow Control Receive Threshold High31513.4.25 Receive Descriptor Base Address Low31613.4.26 Receive Descriptor Base Address High31613.4.27 Receive Descriptor Length31713.4.28 Receive Descriptor Head31713.4.29 Receive Descriptor Tail31813.4.30 Receive Delay Timer Register31813.4.31 Receive Interrupt Absolute Delay Timer31913.4.32 Receive Small Packet Detect Interrupt32013.4.33 Transmit Control Register32013.4.34 Transmit IPG Register32213.4.35 Adaptive IFS Throttle - AIT32413.4.36 Transmit Descriptor Base Address Low32513.4.37 Transmit Descriptor Base Address High32613.4.38 Transmit Descriptor Length32613.4.39 Transmit Descriptor Head32713.4.40 Transmit Descriptor Tail32813.4.41 Transmit Interrupt Delay Value32813.4.42 TX DMA Control (82544GC/EI only)32913.4.43 Transmit Descriptor Control32913.4.44 Transmit Absolute Interrupt Delay Value33113.4.45 TCP Segmentation Pad And Minimum Threshold33213.4.46 Receive Descriptor Control33413.4.47 Receive Checksum Control33513.5 Filter Registers33713.5.1 Multicast Table Array33713.5.2 Receive Address Low33913.5.3 Receive Address High33913.5.4 VLAN Filter Table Array34013.6 Wakeup Registers34113.6.1 Wakeup Control Register34113.6.2 Wakeup Filter Control Register34213.6.3 Wakeup Status Register34313.6.4 IP Address Valid34513.6.5 IPv4 Address Table34613.6.6 IPv6 Address Table34713.6.7 Wakeup Packet Length34813.6.8 Wakeup Packet Memory (128 Bytes)34813.6.9 Flexible Filter Length Table34813.6.10 Flexible Filter Mask Table34913.6.11 Flexible Filter Value Table35013.7 Statistics Registers35013.7.1 CRC Error Count35113.7.2 Alignment Error Count35113.7.3 Symbol Error Count35213.7.4 RX Error Count35213.7.5 Missed Packets Count35313.7.6 Single Collision Count35313.7.7 Excessive Collisions Count35413.7.8 Multiple Collision Count35413.7.9 Late Collisions Count35513.7.10 Collision Count35513.7.11 Defer Count35613.7.12 Transmit with No CRS35613.7.13 Sequence Error Count35713.7.14 Carrier Extension Error Count35713.7.15 Receive Length Error Count35813.7.16 XON Received Count35813.7.17 XON Transmitted Count35913.7.18 XOFF Received Count35913.7.19 XOFF Transmitted Count35913.7.20 FC Received Unsupported Count36013.7.21 Packets Received (64 Bytes) Count36013.7.22 Packets Received (65-127 Bytes) Count36113.7.23 Packets Received (128-255 Bytes) Count36113.7.24 Packets Received (256-511 Bytes) Count36213.7.25 Packets Received (512-1023 Bytes) Count36213.7.26 Packets Received (1024 to Max Bytes) Count36313.7.27 Good Packets Received Count36313.7.28 Broadcast Packets Received Count36413.7.29 Multicast Packets Received Count36413.7.30 Good Packets Transmitted Count36513.7.31 Good Octets Received Count36513.7.32 Good Octets Transmitted Count36613.7.33 Receive No Buffers Count36613.7.34 Receive Undersize Count36713.7.35 Receive Fragment Count36713.7.36 Receive Oversize Count36813.7.37 Receive Jabber Count36813.7.38 Management Packets Received Count36913.7.39 Management Packets Dropped Count137013.7.40 Management Pkts Transmitted Count37013.7.41 Total Octets Received37013.7.42 Total Octets Transmitted37113.7.43 Total Packets Received37213.7.44 Total Packets Transmitted37213.7.45 Packets Transmitted (64 Bytes) Count37313.7.46 Packets Transmitted (65-127 Bytes) Count37313.7.47 Packets Transmitted (128-255 Bytes) Count37413.7.48 Packets Transmitted (256-511 Bytes) Count37413.7.49 Packets Transmitted (512-1023 Bytes) Count37513.7.50 Packets Transmitted (1024 Bytes or Greater) Count37513.7.51 Multicast Packets Transmitted Count37613.7.52 Broadcast Packets Transmitted Count37613.7.53 TCP Segmentation Context Transmitted Count37713.7.54 TCP Segmentation Context Transmit Fail Count37713.8 Diagnostics Registers37813.8.1 Receive Data FIFO Head Register37813.8.2 Receive Data FIFO Tail Register37813.8.3 Receive Data FIFO Head Saved Register37913.8.4 Receive Data FIFO Tail Saved Register37913.8.5 Receive Data FIFO Packet Count38013.8.6 Transmit Data FIFO Head Register38013.8.7 Transmit Data FIFO Tail Register38113.8.8 Transmit Data FIFO Head Saved Register38113.8.9 Transmit Data FIFO Tail Saved Register38213.8.10 Transmit Data FIFO Packet Count38213.8.11 Packet Buffer Memory383General Initialization and Reset Operation 1438514.1 Introduction38514.2 Power Up State38514.3 General Configuration38514.4 Receive Initialization38614.5 Transmit Initialization38714.5.1 Signal Interface39014.5.2 GMII/MII Features not Supported39114.5.3 Avoiding GMII Test Mode(s)39214.5.4 MAC Configuration39214.5.5 Link Setup39314.6 PHY Initialization (10/100/1000 Mb/s Copper Media)39414.7 Reset Operation39514.8 Initialization of Statistics398Diagnostics and Testability 1539915.1 Diagnostics39915.1.1 FIFO State39915.1.2 FIFO Data39915.1.3 Loopback39915.1.3.1 Internal Loopback40015.2 Testability40015.2.1 EXTEST Instruction40115.2.2 SAMPLE/PRELOAD Instruction40115.2.3 IDCODE Instruction40115.2.4 BYPASS Instruction401Appendix (Changes From 82544EI/82544GC) A403Appendix (82540EP/EM and 82545GM/EM Differences) B405Größe: 3,21 MBSeiten: 406Language: EnglishHandbuch öffnen
BenutzerhandbuchInhaltsverzeichnis1. INTRODUCTION41.1 SEE ALSO41.2 COMPATIBILITY42. MODEL NUMBERS53. KEY FEATURES63. SWITCH CAPABILITIES (MODELS 5468/6468)74. OEM DEVELOPER KIT CONTENTS75. SYSTEM REQUIREMENTS96. HARDWARE INFORMATION106.1 BOARD PHOTOS106.2 BOARD LED INDICATORS116.2 BOARD LED INDICATORS126.3 PMC CONNECTOR PIN/SIGNAL DEFINITIONS156.4 PCI CONFIGURATION REGISTERS196.4.1 VENDOR AND DEVICE IDS206.5 EEPROM LISTINGS206.6 DEFAULT REGISTER SETTINGS226.7 ETHERNET FRAME LATENCY247. POWER CONSUMPTION SPECS248. HARDWARE INSTALLATION248.1 INSTALLATION IN PC COMPUTER258.2 EMBEDDED OR COMPACT PCI INSTALLATION259. COPPER CABLING AND CONNECTOR INFO269.1. FIBER CABLE SPECIFICATIONS269.2 COPPER RJ-45 CONNECTOR AND CABLE2710. SOFTWARE DRIVER INSTALLATION2810.1 LINUX DRIVER INSTALLATION AND USAGE2810.2 VXWORKS DRIVER INSTALLATION AND USAGE3510.3 DRIVER UTILITY COMMAND REFERENCE3610.3.1 STATISTICS SHOW FUNCTION3610.3.2 PCI REGISTERS SHOW FUNCTION3710.3.3 MAC REGISTERS SHOW FUNCTION3810.3.4 MAC STATISTICS SHOW FUNCTION3910.3.5 PHY REGISTERS SHOW FUNCTION4110.3.6 EEPROM SHOW FUNCTION4210.3.7 MAC ADDRESS SHOW FUNCTION4310.3.7 MAC ADDRESS SHOW FUNCTION4310.3.8 BUFFER DESCRIPTOR STATUS SHOW FUNCTION4310.3.9 STARTING FRAME GENERATOR4410.3.10 STOPPING FRAME GENERATOR4410.3.11 SWITCH STATUS SHOW FUNCTION4510.4 DPM DRIVER MANAGEMENT API4510.5 SWITCH CONFIGURATION / MANAGEMENT API4711. TESTING AND VERIFICATION4912. SPECIFICATIONS5012.1 ENVIRONMENTAL SPECIFICATIONS5313. WARRANTEE AND SUPPORT INFO54Größe: 876 KBSeiten: 54Language: EnglishHandbuch öffnen
