Benutzerhandbuch (BX80605X3470)InhaltsverzeichnisIntel® Xeon® Processor 3400 Series11 Introduction91.1 Processor Feature Details111.1.1 Supported Technologies111.2 Interfaces121.2.1 System Memory Support121.2.2 PCI Express*131.2.3 Direct Media Interface (DMI)141.2.4 Platform Environment Control Interface (PECI)141.3 Power Management Support151.3.1 Processor Core151.3.2 System151.3.3 Memory Controller151.3.4 PCI Express*151.4 Thermal Management Support151.5 Package151.6 Terminology161.7 Related Documents182 Interfaces192.1 System Memory Interface192.1.1 System Memory Technology Supported192.1.2 System Memory Timing Support202.1.3 System Memory Organization Modes202.1.4 Rules for Populating Memory Slots222.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)232.1.6 System Memory Pre-Charge Power Down Support Details232.2 PCI Express* Interface242.2.1 PCI Express* Architecture242.2.2 PCI Express* Configuration Mechanism262.2.3 PCI Express* Ports and Bifurcation262.3 Direct Media Interface (DMI)272.3.1 DMI Error Flow272.3.2 Processor/PCH Compatibility Assumptions272.3.3 DMI Link Down272.4 Platform Environment Control Interface (PECI)282.5 Interface Clocking282.5.1 Internal Clocking Requirements283 Technologies293.1 Intel® Virtualization Technology293.1.1 Intel® VT-x Objectives293.1.2 Intel® VT-x Features293.1.3 Intel® VT-d Objectives303.1.4 Intel® VT-d Features303.1.5 Intel® VT-d Features Not Supported313.2 Intel® Trusted Execution Technology (Intel® TXT)313.3 Intel® Hyper-Threading Technology323.4 Intel® Turbo Boost Technology324 Power Management334.1 ACPI States Supported334.1.1 System States334.1.2 Processor Core/Package Idle States334.1.3 Integrated Memory Controller States334.1.4 PCI Express* Link States344.1.5 Interface State Combinations344.2 Processor Core Power Management344.2.1 Enhanced Intel® SpeedStep® Technology354.2.2 Low-Power Idle States354.2.3 Requesting Low-Power Idle States374.2.4 Core C-states374.2.5 Package C-States394.3 IMC Power Management414.3.1 Disabling Unused System Memory Outputs414.3.2 DRAM Power Management and Initialization424.4 PCI Express* Power Management435 Thermal Management456 Signal Description476.1 System Memory Interface486.2 Memory Reference and Compensation506.3 Reset and Miscellaneous Signals506.4 PCI Express* Based Interface Signals516.5 DMI — Processor to PCH Serial Interface526.6 PLL Signals526.7 Intel® Flexible Display Interface Signals526.8 JTAG/ITP Signals536.9 Error and Thermal Protection546.10 Power Sequencing556.11 Processor Core Power Signals556.12 Graphics and Memory Core Power Signals576.13 Ground and NCTF586.14 Processor Internal Pull Up/Pull Down587 Electrical Specifications597.1 Power and Ground Lands597.2 Decoupling Guidelines597.2.1 Voltage Rail Decoupling597.3 Processor Clocking (BCLK[0], BCLK#[0])607.3.1 PLL Power Supply607.4 VCC Voltage Identification (VID)607.5 Reserved or Unused Signals647.6 Signal Groups647.7 Test Access Port (TAP) Connection677.8 Absolute Maximum and Minimum Ratings677.9 DC Specifications687.9.1 Voltage and Current Specifications687.10 Platform Environmental Control Interface (PECI) DC Specifications747.10.1 DC Characteristics757.10.2 Input Device Hysteresis758 Processor Land and Signal Information778.1 Processor Land Assignments77Größe: 870 KBSeiten: 96Language: EnglishHandbuch öffnen