Benutzerhandbuch für Konica Minolta PCI-1712L

Inhaltsverzeichnis

• Contents

  5
  • 1. Introduction

    13
  • 1.1 Features

    13
  • 1.2 Installation Guide

    15
  • 1.3 Accessories

    17
  • 2. Installation

    19
  • 2.1 Unpacking

    19
  • 2.2 Driver Installation

    20
  • 2.3 Hardware Installation

    21
  • 2.4 Device Setup & Configuration

    24
  • 2.5 Device Testing

    27
  • 3. Signal Connections

    31
  • 3.1 Overview

    31
  • 3.2 I/O Connector

    31
  • 3.3 Analog Input Connections

    36
  • 3.4 Analog Output Connections

    39
  • 3.5 Field Wiring Considerations

    40
  • 4. Software Overview

    41
  • 4.1 Programming Choices

    41
  • 4.2 DLL Driver Programming Roadmap

    42
  • 5. Principles of Operation

    45
  • 5.1 Analog Input Features

    45
  • 5.2 Analog Output Features

    52
  • 5.3 Digital I/O Features

    55
  • 5.4 Counter/Timer Features

    56
  • 6. Calibration

    67
  • 6.1 VR Assignment

    67
  • 6.2 A/D Calibration

    68
  • 6.3 D/A Calibration

    69
  • 6.4 Calibration Utility

    70
  • Appendix A. Specification

    81
  • Appendix B. Block Diagram

    85
  • Appendix C. Screw-terminal Board

    87
  • C. 1 Introduction

    87
  • C. 2 Features

    87
  • C. 3 Board Layout

    87
  • C.4 Pin Assignment

    88
  • C.5 Single-ended Connections

    89
  • C.6 Differential Connections

    90
  • Appendix D. Register Structure and Format

    91
  • D.1 Overview

    91
  • D.2 I/O Port Address Map

    91
  • D.3 A/D Single Value Acquisition - Write BASE+0

    95
  • D.4 Channel and A/D data - Read BASE + 0

    95
  • D.5 A/D Channel Range Setting - Write BASE+2

    96
  • D.6 MUX Control - Write BASE+4

    97
  • D.7 A/D Control/Status Register - Write/Read BASE+6

    99
  • D.8 Clear interrupt and FIFO - Write BASE+8

    101
  • D. 9 Interrupt and FIFO status - Read BASE+8

    102
  • D.10 D/A control/status register - Write/Read BASE+A

    103
  • D.11 D/A Channel 0/1 Data - Write BASE+C/E

    105
  • D.12 82C54 Counter Chip 0 - Write/Read BASE+10 to 16

    106
  • D.13 82C54 counter chip 1 - Write/Read BASE+18 to 1E

    107
  • D.14 Counter gate and clock control/status - Write/ Read BASE+20 to 26

    108
  • D.15 Digital I/O registers - Write/Read BASE+28

    111
  • D.16 Digital I/O configuration registers - Write/Read BASE+2A

    112
  • D.17 Calibration command registers - Write BASE+2C

    112
  • D.18 D/A Channel Data for Continuous Output Operation Mode - Write BASE+30

    114
• Figures

  8
  • Figure 2-1: The Setup Screen of Advantech Automation Software

    20
  • Figure 2-2: Different options for Driver Setup

    21
  • Figure 2-3: The device name listed on the Device Manager

    23
  • Figure 2-4: The Advantech Device Installation utility program

    24
  • Figure 2-5: The I/O Device Installation dialog box

    24
  • Figure 2-6: The "Device(s) Found" dialog box

    25
  • Figure 2-7: The Device Setting dialog box

    25
  • Figure 2-8: The Device Name appearing on the list of devices box

    26
  • Figure 2-9: Analog Input tab on the Device Test dialog box

    27
  • Figure 2-10: Analog Input tab on the Device Test dialog box

    28
  • Figure 2-11: Analog Output tab on the Device Test dialog box

    28
  • Figure 2-12: Digital Input tab on the Device Test dialog box

    29
  • Figure 2-13: Digital Output tab on the Device Test dialog box

    29
  • Figure 2-14: Digital output tab on the Device Test dialog box

    30
  • Figure 3-1: I/O connector pin assignments for the PCI-1712/1712L

    32
  • Figure 3-2: Single-ended input channel connection

    36
  • Figure 3-3: Differential input channel connection - ground reference signal source

    37
  • Figure 3-4: Differential input channel connection - floating signal source

    38
  • Figure 3-5: Analog output connections

    39
  • Figure 5-1: Post-Trigger Acquisition Mode

    47
  • Figure 5-2: Delay-Trigger Acquisition Mode

    47
  • Figure 5-3: About-Trigger Acquisition Mode

    48
  • Figure 5-4: Pre-Trigger Acquisition Mode

    49
  • Figure 5-5: PCI-1712/1712L Sample Clock Source

    50
  • Figure 5-6: Frequency measurement

    61
  • Figure 6-1: PCI-1712/1712L VR1 & TP5

    67
  • Figure 6-2: Selecting the device you want to calibrate

    70
  • Figure 6-3: Warning message before start calibration

    71
  • Figure 6-4: Auto A/D Calibration Dialog Box

    71
  • Figure 6-5: A/D Calibration Procedure 1

    72
  • Figure 6-6: A/D Calibration Procedure 2

    72
  • Figure 6-7: A/D Calibration Procedure 3

    73
  • Figure 6-8: A/D Calibration is finished

    73
  • Figure 6-9: Range Selection in D/A Calibration

    74
  • Figure 6-10: Calibrating D/A Channel 0

    74
  • Figure 6-11: Calibrating D/A Channel 1

    75
  • Figure 6-12: D/A Calibration is finished

    75
  • Figure 6-13: Selecting Input Rage in Manual A/D Calibration panel

    76
  • Figure 6-14: Adjusting registers

    77
  • Figure 6-15: Selecting D/A Range and

    78
  • Figure 6-16: Selecting D/A Range and Choosing Output Voltage

    78
  • Figure 6-17: Adjusting registers

    79
  • Figure C-1: PCLD-8712 board layout

    87
  • Figure C-2: CN2 pin assignments for the PCLD-8712

    88
• Tables

  10
  • Table 3-1: I/O Connector Signal Description (Part 1)

    33
  • Table 3-1: I/O Connector Signal Description (Part 2)

    34
  • Table 3-1: I/O Connector Signal Description (Part 3)

    35
  • Table 5-1: Gains and Analog Input Range

    45
  • Table 5-2: Analog Input Data Format

    51
  • Table 5-3: The corresponding Full Scale values for various Input Voltage Ranges

    51
  • Table 5-4: Analog Output Data Format

    55
  • Table 5-5: The corresponding Full Scale values for various Output Voltage Ranges

    55
  • Table D-1: PCI-1712/1712L register format (Part 1)

    92
  • Table D-1: PCI-1712/1712L register format (Part 2)

    93
  • Table D-1: PCI-1712/1712L register format (Part 3)

    94
  • Table D-2: Register for channel number and A/D data

    95
  • Table D-3: Register for A/D channel range setting

    96
  • Table D-4: Gain Codes for the PCI-1712/1712L

    97
  • Table D-5: Register for multiplexer control

    97
  • Table D-6: Register for A/D control/status

    99
  • Table D-7: Analog Input Acquisition Mode

    100
  • Table D-8: Register for clear interrupt and FIFO

    101
  • Table D-9: Register for interrupt and FIFO status

    102
  • Table D-10: Register for D/A control

    103
  • Table D-11: Analog output operation mode

    104
  • Table D-12: Register for D/A channel 0/1 data

    105
  • Table D-13: Register for 82C54 counter chip 0

    106
  • Table D-14: Register for 82C54 counter chip 1

    107
  • Table D-15: Register for counter gate and clock control/status

    108
  • Table D-16 : Table of Cn1 to Cn0 register

    108
  • Table D-17: Table of Gn1 to Gn0 register

    109
  • Table D-18: Table for CLK_SEL1 to CLK_SEL0 register

    111
  • Table D-19: Register for Digital I/O

    111
  • Table D-20: Register for digital I/O configuration

    112
  • Table D-21: Register for digital I/O configuration

    112
  • Table D-22: Register for calibration command

    112
  • Table D-23: Calibration command

    113
  • Table D-24: Register for D/A channel data

    114