Benutzerhandbuch für Microchip Technology AC244044

Inhaltsverzeichnis

• High-Performance RISC CPU:

  3
• Flexible Oscillator Structure:

  3
• Special Microcontroller Features:

  3
• Extreme Low-Power Management PIC16LF1825/1829 with XLP:

  3
• Analog Features:

  3
• Peripheral Highlights:

  3
• Peripheral Highlights (Continued):

  4
• Table of Contents

  9
• Most Current Data Sheet

  10
• Errata

  10
• Customer Notification System

  10
• 1.0 Device Overview

  11
  • TABLE 1-1: Device Peripheral Summary

    11
  • FIGURE 1-1: PIC16(L)F1825/1829 Block Diagram

    12
  • TABLE 1-2: PIC16(L)F1825 Pinout Description

    13
  • TABLE 1-3: PIC16(L)F1829 Pinout Description

    16
• 2.0 Enhanced Mid-range CPU

  19
  • 2.1 Automatic Interrupt Context Saving

    19
  • 2.2 16-level Stack with Overflow and Underflow

    19
  • 2.3 File Select Registers

    19
  • 2.4 Instruction Set

    19
    • FIGURE 2-1: Core Block Diagram

      20
• 3.0 Memory Organization

  21
  • 3.1 Program Memory Organization

    21
    • TABLE 3-1: Device Sizes and Addresses

      21
    • FIGURE 3-1: Program Memory Map And Stack For PIC16(L)F1825/1829

      22
    • 3.1.1 Reading Program Memory as Data

      22
      • EXAMPLE 3-1: RETLW Instruction

        22
      • EXAMPLE 3-2: Accessing Program Memory Via FSR

        23
  • 3.2 Data Memory Organization

    23
    • 3.2.1 Core Registers

      23
      • Register 3-1: STATUS: STATUS Register

        24
    • 3.2.2 Special Function Register

      25
    • 3.2.3 General Purpose RAM

      25
    • 3.2.4 Common RAM

      25
      • FIGURE 3-2: Banked Memory Partitioning

        25
    • 3.2.5 Device Memory Maps

      25
      • TABLE 3-2: Memory Map Tables

        25
      • TABLE 3-3: PIC16(L)F1825/1829 Memory Map, Banks 0-7

        26
      • TABLE 3-4: PIC16(L)F1825/1829 Memory Map, Banks 8-15

        27
      • TABLE 3-5: PIC16(L)F1825/1829 Memory Map, Banks 16-23

        28
      • TABLE 3-6: PIC16(L)F1825/1829 Memory Map, Banks 24-31

        29
      • TABLE 3-7: PIC16(L)F1825/1829 Memory Map, Bank 31

        30
    • 3.2.6 Special Function Registers Summary

      30
      • TABLE 3-8: Special Function Register Summary

        31
  • 3.3 PCL and PCLATH

    42
    • FIGURE 3-3: Loading of PC in Different Situations

      42
    • 3.3.1 Modifying PCL

      42
    • 3.3.2 Computed goto

      42
    • 3.3.3 Computed Function Calls

      42
    • 3.3.4 Branching

      42
  • 3.4 Stack

    43
    • 3.4.1 Accessing the Stack

      43
      • FIGURE 3-4: Accessing the Stack Example 1

        43
      • FIGURE 3-5: Accessing the Stack Example 2

        44
      • FIGURE 3-6: Accessing the Stack Example 3

        44
      • FIGURE 3-7: Accessing the Stack Example 4

        45
    • 3.4.2 Overflow/Underflow Reset

      45
  • 3.5 Indirect Addressing

    45
    • FIGURE 3-8: Indirect Addressing

      46
    • 3.5.1 Traditional Data Memory

      47
      • FIGURE 3-9: Traditional Data Memory Map

        47
    • 3.5.2 Linear Data Memory

      48
      • FIGURE 3-10: Linear Data Memory Map

        48
    • 3.5.3 Program Flash Memory

      48
      • FIGURE 3-11: Program Flash Memory Map

        48
• 4.0 Device Configuration

  49
  • 4.1 Configuration Words

    49
    • Register 4-1: Configuration Word 1

      50
    • Register 4-2: Configuration Word 2

      52
  • 4.2 Code Protection

    53
    • 4.2.1 Program Memory Protection

      53
    • 4.2.2 Data EEPROM Protection

      53
  • 4.3 Write Protection

    53
  • 4.4 User ID

    53
  • 4.5 Device ID and Revision ID

    54
    • Register 4-3: DEVICEID: Device ID Register(1)

      54
• 5.0 Oscillator Module (With Fail-Safe Clock Monitor)

  55
  • 5.1 Overview

    55
    • FIGURE 5-1: Simplified PIC® MCU Clock Source Block Diagram

      56
  • 5.2 Clock Source Types

    57
    • 5.2.1 External Clock Sources

      57
      • FIGURE 5-2: External Clock (EC) Mode Operation

        57
      • FIGURE 5-3: Quartz Crystal Operation (LP, XT or HS Mode)

        58
      • FIGURE 5-4: Ceramic Resonator Operation (XT or HS Mode)

        58
      • FIGURE 5-5: Quartz Crystal Operation (Timer1 Oscillator)

        59
      • FIGURE 5-6: External RC Modes

        60
    • 5.2.2 Internal Clock Sources

      60
      • FIGURE 5-7: Internal Oscillator Switch Timing

        64
  • 5.3 Clock Switching

    65
    • 5.3.1 System Clock Select (SCS) BitS

      65
    • 5.3.2 Oscillator Start-up Timer Status (OSTS) Bit

      65
    • 5.3.3 Timer1 Oscillator

      65
    • 5.3.4 Timer1 Oscillator Ready (T1OSCR) Bit

      65
  • 5.4 Two-Speed Clock Start-up Mode

    66
    • 5.4.1 Two-Speed Start-up Mode Configuration

      66
      • TABLE 5-1: Oscillator Switching Delays

        66
    • 5.4.2 Two-Speed Start-up Sequence

      67
    • 5.4.3 Checking Two-Speed Clock Status

      67
      • FIGURE 5-8: Two-Speed Start-up

        67
  • 5.5 Fail-Safe Clock Monitor

    68
    • FIGURE 5-9: FSCM Block Diagram

      68
    • 5.5.1 Fail-Safe Detection

      68
    • 5.5.2 Fail-Safe Operation

      68
    • 5.5.3 Fail-Safe Condition Clearing

      68
    • 5.5.4 Reset or Wake-up from Sleep

      68
      • FIGURE 5-10: FSCM Timing Diagram

        69
  • 5.6 Oscillator Control Registers

    70
    • Register 5-1: OSCCON: Oscillator Control Register

      70
    • Register 5-2: OSCSTAT: Oscillator Status Register

      71
    • Register 5-3: OSCTUNE: Oscillator Tuning Register

      72
    • TABLE 5-2: Summary of Registers Associated with Clock Sources

      72
    • TABLE 5-3: Summary of Configuration Word with Clock Sources

      72
• 6.0 Reference Clock Module

  73
  • 6.1 Slew Rate

    73
  • 6.2 Effects of a Reset

    73
  • 6.3 Conflicts with the CLKR Pin

    73
    • 6.3.1 Oscillator Modes

      73
    • 6.3.2 CLKOUT Function

      73
  • 6.4 Operation During Sleep

    73
  • 6.5 Reference Clock Control Register

    74
    • Register 6-1: CLKRCON: Reference Clock Control Register

      74
    • TABLE 6-1: Summary of Registers Associated with Reference Clock Sources

      75
    • TABLE 6-2: Summary of Configuration Word with Reference Clock Sources

      75
• 7.0 Resets

  77
  • FIGURE 7-1: Simplified Block Diagram Of On-Chip Reset Circuit

    77
  • 7.1 Power-on Reset (POR)

    78
    • 7.1.1 Power-up Timer (PWRT)

      78
  • 7.2 Brown-Out Reset (BOR)

    78
    • TABLE 7-1: BOR Operating Modes

      78
    • 7.2.1 BOR is Always On

      78
    • 7.2.2 BOR is Off in Sleep

      78
    • 7.2.3 BOR Controlled by Software

      78
      • FIGURE 7-2: Brown-Out Situations

        79
      • Register 7-1: BORCON: Brown-out Reset Control Register

        79
  • 7.3 MCLR

    80
    • TABLE 7-2: MCLR Configuration

      80
    • 7.3.1 MCLR Enabled

      80
    • 7.3.2 MCLR Disabled

      80
  • 7.4 Watchdog Timer (WDT) Reset

    80
  • 7.5 RESET Instruction

    80
  • 7.6 Stack Overflow/Underflow Reset

    80
  • 7.7 Programming Mode Exit

    80
  • 7.8 Power-Up Timer

    80
  • 7.9 Start-up Sequence

    80
    • FIGURE 7-3: Reset Start-up Sequence

      81
  • 7.10 Determining the Cause of a Reset

    82
    • TABLE 7-3: Reset Status Bits and Their Significance

      82
    • TABLE 7-4: Reset Condition for Special Registers(2)

      82
  • 7.11 Power Control (PCON) Register

    83
    • Register 7-2: PCON: Power Control Register

      83
    • TABLE 7-5: Summary of Registers Associated with Resets(1)

      84
• 8.0 Interrupts

  85
  • FIGURE 8-1: Interrupt Logic

    85
  • 8.1 Operation

    86
  • 8.2 Interrupt Latency

    86
    • FIGURE 8-2: Interrupt Latency

      87
    • FIGURE 8-3: INT Pin Interrupt Timing

      88
  • 8.3 Interrupts During Sleep

    89
  • 8.4 INT Pin

    89
  • 8.5 Automatic Context Saving

    89
  • 8.6 Interrupt Control Registers

    90
    • 8.6.1 INTCON Register

      90
      • Register 8-1: INTCON: Interrupt Control Register

        90
    • 8.6.2 PIE1 Register

      91
      • Register 8-2: PIE1: Peripheral Interrupt Enable Register 1

        91
    • 8.6.3 PIE2 Register

      92
      • Register 8-3: PIE2: Peripheral Interrupt Enable Register 2

        92
    • 8.6.4 PIE3 Register

      93
      • Register 8-4: PIE3: Peripheral Interrupt Enable Register 3

        93
    • 8.6.5 PIE4 Register(1)

      94
      • Register 8-5: PIE4: Peripheral Interrupt Enable Register 4(1)

        94
    • 8.6.6 PIR1 Register

      95
      • Register 8-6: PIR1: Peripheral Interrupt Request Register 1

        95
    • 8.6.7 PIR2 Register

      96
      • Register 8-7: PIR2: Peripheral Interrupt Request Register 2

        96
    • 8.6.8 PIR3 Register

      97
      • Register 8-8: PIR3: Peripheral Interrupt Request Register 3

        97
    • 8.6.9 PIR4 Register(1)

      98
      • Register 8-9: PIR4: Peripheral Interrupt Request Register 4(1)

        98
      • TABLE 8-1: Summary of Registers Associated with Interrupts

        98
• 9.0 Power-Down Mode (Sleep)

  99
  • 9.1 Wake-up from Sleep

    99
    • 9.1.1 Wake-up Using Interrupts

      99
      • FIGURE 9-1: Wake-up From Sleep Through Interrupt

        100
      • TABLE 9-1: Summary of Registers Associated with Power-Down Mode

        100
• 10.0 Watchdog Timer

  101
  • FIGURE 10-1: Watchdog Timer Block Diagram

    101
  • 10.1 Independent Clock Source

    102
  • 10.2 WDT Operating Modes

    102
    • 10.2.1 WDT Is Always On

      102
    • 10.2.2 WDT Is Off In Sleep

      102
    • 10.2.3 WDT Controlled By Software

      102
      • TABLE 10-1: WDT Operating Modes

        102
  • 10.3 Time-Out Period

    102
  • 10.4 Clearing the WDT

    102
  • 10.5 Operation During Sleep

    102
    • TABLE 10-2: WDT Clearing Conditions

      102
  • 10.6 Watchdog Control Register

    103
    • Register 10-1: WDTCON: Watchdog Timer Control Register

      103
    • TABLE 10-3: Summary of Registers Associated with Watchdog Timer

      104
    • TABLE 10-4: Summary of Configuration Word with Watchdog Timer

      104
• 11.0 Data EEPROM and Flash Program Memory Control

  105
  • 11.1 EEADRL and EEADRH Registers

    105
    • 11.1.1 EECON1 and EECON2 Registers

      105
  • 11.2 Using the Data EEPROM

    106
    • 11.2.1 Reading the Data EEPROM Memory

      106
      • EXAMPLE 11-1: Data EEPROM Read

        106
    • 11.2.2 Writing to the Data EEPROM Memory

      106
    • 11.2.3 Protection Against Spurious Write

      106
    • 11.2.4 Data EEPROM Operation During Code-Protect

      106
      • EXAMPLE 11-2: Data EEPROM Write

        107
      • FIGURE 11-1: Flash Program Memory Read Cycle Execution

        107
  • 11.3 Flash Program Memory Overview

    108
    • TABLE 11-1: Flash Memory Organization By Device

      108
    • 11.3.1 Reading the Flash Program Memory

      108
      • EXAMPLE 11-3: Flash Program Memory Read

        109
    • 11.3.2 Erasing Flash Program Memory

      110
    • 11.3.3 Writing to Flash Program Memory

      110
      • FIGURE 11-2: Block Writes to Flash Program Memory With 32 Write Latches

        111
      • EXAMPLE 11-4: Erasing One Row of Program Memory

        112
      • EXAMPLE 11-5: Writing to Flash Program Memory

        113
  • 11.4 Modifying Flash Program Memory

    114
  • 11.5 User ID, Device ID and Configuration Word Access

    114
    • TABLE 11-2: User ID, Device ID and Configuration Word Access (cfgs = 1)

      114
  • 11.6 Write Verify

    115
    • EXAMPLE 11-6: EEPROM Write Verify

      115
  • 11.7 EEPROM and Flash Control Registers

    116
    • Register 11-1: EEDATL: EEPROM Low Byte Data Register

      116
    • Register 11-2: EEDATH: EEPROM Data High Byte Register

      116
    • Register 11-3: EEADRL: EEPROM Address Register

      116
    • Register 11-4: EEADRH: EEPROM Address High Byte Register

      116
    • Register 11-5: EECON1: EEPROM Control 1 Register

      117
    • Register 11-6: EECON2: EEPROM Control 2 Register

      118
    • TABLE 11-3: Summary of Registers Associated with Data EEPROM

      118
• 12.0 I/O Ports

  119
  • TABLE 12-1: Port Availability Per Device

    119
  • FIGURE 12-1: Generic I/O Port Operation

    119
  • EXAMPLE 12-1: Initializing PORTA

    119
  • 12.1 Alternate Pin Function

    120
    • Register 12-1: APFCON0: Alternate Pin Function Control Register 0

      121
    • Register 12-2: APFCON1: Alternate Pin Function Control Register 1

      122
  • 12.2 PORTA Registers

    123
    • 12.2.1 ANSELA Register

      123
      • EXAMPLE 12-2: Initializing PORTA

        123
    • 12.2.2 PORTA Functions and Output Priorities

      124
      • TABLE 12-2: PORTA Output Priority

        124
      • Register 12-3: PORTA: PORTA Register

        125
      • Register 12-4: TRISA: PORTA Tri-State Register

        125
      • Register 12-5: LATA: PORTA Data Latch Register

        126
      • Register 12-6: ANSELA: PORTA Analog Select Register

        126
      • Register 12-7: WPUA: Weak Pull-up PORTA Register

        127
      • Register 12-8: INLVLA: PORTA Input Level Control Register

        127
      • TABLE 12-3: Summary of Registers Associated with PORTA

        128
      • TABLE 12-4: Summary of Configuration Word with PORTA

        128
  • 12.3 PORTB Registers (PIC16(L)F1829 only)

    129
    • 12.3.1 ANSELB Register

      129
    • 12.3.2 PORTB Functions and Output Priorities

      130
      • TABLE 12-5: PORTB Output Priority

        130
      • Register 12-9: PORTB: PORTB Register

        131
      • Register 12-10: TRISB: PORTB Tri-State Register

        131
      • Register 12-11: LATB: PORTB Data Latch Register

        131
      • Register 12-12: ANSELB: PORTB Analog Select Register

        132
      • Register 12-13: WPUB: Weak Pull-up PORTB Register

        132
      • Register 12-14: INLVLB: PORTB Input Level Control Register

        132
      • TABLE 12-6: Summary of Registers Associated with PORTB(1)

        133
  • 12.4 PORTC Registers

    134
    • 12.4.1 ANSELC Register

      134
    • 12.4.2 PORTC Functions and Output Priorities

      135
      • TABLE 12-7: PORTC Output Priority

        135
      • Register 12-15: PORTC: PORTC Register

        136
      • Register 12-16: TRISC: PORTC Tri-State Register

        136
      • Register 12-17: LATC: PORTC Data Latch Register

        136
      • Register 12-18: ANSELC: PORTC Analog Select Register

        137
      • Register 12-19: WPUC: Weak Pull-up PORTC Register

        137
      • Register 12-20: INLVLC: PORTC Input Level Control Register

        138
      • TABLE 12-8: Summary of Registers Associated with PORTC

        138
• 13.0 Interrupt-on-Change

  139
  • 13.1 Enabling the Module

    139
  • 13.2 Individual Pin Configuration

    139
  • 13.3 Interrupt Flags

    139
  • 13.4 Clearing Interrupt Flags

    139
    • EXAMPLE 13-1: Clearing Interrupt Flags (PORTA Example)

      139
  • 13.5 Operation in Sleep

    139
    • FIGURE 13-1: Interrupt-On-Change Block Diagram (PORTA Example)

      140
  • 13.6 Interrupt-on-Change Registers

    140
    • Register 13-1: IOCAP: Interrupt-on-Change PORTA Positive Edge Register

      140
    • Register 13-2: IOCAN: Interrupt-on-Change PORTA Negative Edge Register

      141
    • Register 13-3: IOCAF: Interrupt-on-Change PORTA Flag Register

      141
    • Register 13-4: IOCBP: Interrupt-on-Change PORTB Positive Edge Register (PIC16(L)F1829 only)

      141
    • Register 13-5: IOCBN: Interrupt-on-Change PORTB Negative Edge Register (PIC16(L)F1829 only)

      142
    • Register 13-6: IOCBF: Interrupt-on-Change PORTB Flag Register (PIC16(L)F1829 only)

      142
    • TABLE 13-1: Summary of Registers Associated with Interrupt-on-Change

      143
• 14.0 Fixed Voltage Reference (FVR)

  145
  • 14.1 Independent Gain Amplifiers

    145
  • 14.2 FVR Stabilization Period

    145
    • FIGURE 14-1: Voltage Reference Block Diagram

      145
  • 14.3 FVR Control Registers

    146
    • Register 14-1: FVRCON: Fixed Voltage Reference Control Register

      146
    • TABLE 14-1: Summary of Registers Associated with the Fixed Voltage Reference

      146
• 15.0 Temperature Indicator Module

  147
  • 15.1 Circuit Operation

    147
    • EQUATION 15-1: Vout Ranges

      147
    • FIGURE 15-1: Temperature Circuit Diagram

      147
  • 15.2 Minimum Operating Vdd vs. Minimum Sensing Temperature

    147
    • TABLE 15-1: Recommended Vdd vs. Range

      147
  • 15.3 Temperature Output

    147
  • 15.4 ADC Acquisition Time

    147
• 16.0 Analog-to-Digital Converter (ADC) Module

  149
  • FIGURE 16-1: ADC Block Diagram

    149
  • 16.1 ADC Configuration

    150
    • 16.1.1 Port Configuration

      150
    • 16.1.2 Channel Selection

      150
    • 16.1.3 ADC Voltage Reference

      150
    • 16.1.4 Conversion Clock

      150
      • TABLE 16-1: ADC Clock Period (Tad) Vs. Device Operating Frequencies

        151
      • FIGURE 16-2: Analog-to-Digital Conversion Tad Cycles

        151
    • 16.1.5 Interrupts

      152
    • 16.1.6 Result Formatting

      152
      • FIGURE 16-3: 10-Bit A/D Conversion Result Format

        152
  • 16.2 ADC Operation

    153
    • 16.2.1 Starting a Conversion

      153
    • 16.2.2 Completion of a Conversion

      153
    • 16.2.3 Terminating a Conversion

      153
    • 16.2.4 ADC Operation During Sleep

      153
    • 16.2.5 Special Event Trigger

      153
      • TABLE 16-2: Special Event Trigger

        153
    • 16.2.6 A/D Conversion Procedure

      154
      • EXAMPLE 16-1: A/D Conversion

        154
    • 16.2.7 ADC Register Definitions

      155
      • Register 16-1: ADCON0: A/D Control Register 0

        155
      • Register 16-2: ADCON1: A/D Control Register 1

        156
      • Register 16-3: ADRESH: ADC Result Register High (ADRESH) ADFM = 0

        157
      • Register 16-4: ADRESL: ADC Result Register Low (ADRESL) ADFM = 0

        157
      • Register 16-5: ADRESH: ADC Result Register High (ADRESH) ADFM = 1

        158
      • Register 16-6: ADRESL: ADC Result Register Low (ADRESL) ADFM = 1

        158
  • 16.3 A/D Acquisition Requirements

    159
    • EQUATION 16-1: Acquisition Time Example

      159
    • FIGURE 16-4: Analog Input Model

      160
    • FIGURE 16-5: ADC Transfer Function

      160
    • TABLE 16-3: Summary of Registers Associated with ADC

      161
• 17.0 Digital-to-Analog Converter (DAC) Module

  163
  • 17.1 Output Voltage Selection

    163
    • EQUATION 17-1: DAC Output Voltage

      163
  • 17.2 Ratiometric Output Level

    163
  • 17.3 DAC Voltage Reference Output

    163
    • FIGURE 17-1: Digital-to-Analog Converter Block Diagram

      164
    • FIGURE 17-2: Voltage Reference Output Buffer Example

      164
  • 17.4 Low-Power Voltage State

    165
    • 17.4.1 Output Clamped to Positive Voltage Source

      165
    • 17.4.2 Output Clamped to Negative Voltage Source

      165
      • FIGURE 17-3: Output Voltage Clamping Examples

        165
  • 17.5 Operation During Sleep

    165
  • 17.6 Effects of a Reset

    165
  • 17.7 DAC Control Registers

    166
    • Register 17-1: DACCON0: Voltage Reference Control Register 0

      166
    • Register 17-2: DACCON1: Voltage Reference Control Register 1

      166
    • TABLE 17-1: Summary of Registers Associated with the DAC Module

      167
• 18.0 SR Latch

  169
  • 18.1 Latch Operation

    169
  • 18.2 Latch Output

    169
  • 18.3 Effects of a Reset

    169
    • FIGURE 18-1: SR Latch Simplified Block Diagram

      170
    • TABLE 18-1: SRCLK Frequency Table

      171
    • Register 18-1: SRCON0: SR Latch Control 0 Register

      171
    • Register 18-2: SRCON1: SR Latch Control 1 Register

      172
    • TABLE 18-2: Summary of Registers Associated with SR Latch Module

      173
• 19.0 Comparator Module

  175
  • 19.1 Comparator Overview

    175
    • FIGURE 19-1: Single Comparator

      175
    • FIGURE 19-2: Comparator Module Simplified Block Diagram

      175
  • 19.2 Comparator Control

    176
    • 19.2.1 Comparator Enable

      176
    • 19.2.2 Comparator Output Selection

      176
    • 19.2.3 Comparator Output Polarity

      176
      • TABLE 19-1: Comparator Output State vs. Input Conditions

        176
    • 19.2.4 Comparator Speed/Power Selection

      176
  • 19.3 Comparator Hysteresis

    176
  • 19.4 Timer1 Gate Operation

    177
    • 19.4.1 Comparator Output Synchronization

      177
  • 19.5 Comparator Interrupt

    177
  • 19.6 Comparator Positive Input Selection

    177
  • 19.7 Comparator Negative Input Selection

    177
  • 19.8 Comparator Response Time

    177
  • 19.9 Interaction with ECCP Logic

    178
  • 19.10 Analog Input Connection Considerations

    178
    • FIGURE 19-3: Analog Input Model

      178
    • Register 19-1: CMxCON0: Comparator cx Control Register 0

      179
    • Register 19-2: CMxCON1: Comparator Cx Control Register 1

      180
    • Register 19-3: CMOUT: Comparator Output Register

      180
    • TABLE 19-2: Summary of Registers Associated with Comparator Module

      181
• 20.0 Timer0 Module

  183
  • 20.1 Timer0 Operation

    183
    • 20.1.1 8-bit Timer Mode

      183
    • 20.1.2 8-Bit Counter Mode

      183
      • FIGURE 20-1: Block Diagram of the Timer0

        183
    • 20.1.3 Software Programmable Prescaler

      184
    • 20.1.4 Timer0 Interrupt

      184
    • 20.1.5 8-Bit Counter Mode Synchronization

      184
    • 20.1.6 Operation During Sleep

      184
  • 20.2 Option and Timer0 Control Register

    185
    • Register 20-1: OPTION_REG: Option Register

      185
    • TABLE 20-1: Summary of Registers Associated with Timer0

      185
• 21.0 Timer1 Module with Gate Control

  187
  • FIGURE 21-1: Timer1 Block Diagram

    187
  • 21.1 Timer1 Operation

    188
    • TABLE 21-1: Timer1 Enable Selections

      188
  • 21.2 Clock Source Selection

    188
    • 21.2.1 Internal Clock Source

      188
    • 21.2.2 External Clock Source

      188
      • TABLE 21-2: Clock Source Selections

        188
  • 21.3 Timer1 Prescaler

    189
  • 21.4 Timer1 Oscillator

    189
  • 21.5 Timer1 Operation in Asynchronous Counter Mode

    189
    • 21.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode

      189
  • 21.6 Timer1 Gate

    189
    • 21.6.1 Timer1 Gate Enable

      189
      • TABLE 21-3: Timer1 Gate Enable Selections

        189
    • 21.6.2 Timer1 Gate Source Selection

      190
      • TABLE 21-4: Timer1 Gate Sources

        190
    • 21.6.3 Timer1 Gate Toggle Mode

      190
    • 21.6.4 Timer1 Gate Single-Pulse Mode

      190
    • 21.6.5 Timer1 Gate Value Status

      190
    • 21.6.6 Timer1 Gate Event Interrupt

      190
  • 21.7 Timer1 Interrupt

    191
  • 21.8 Timer1 Operation During Sleep

    191
  • 21.9 ECCP/CCP Capture/Compare Time Base

    191
  • 21.10 ECCP/CCP Special Event Trigger

    191
    • FIGURE 21-2: Timer1 Incrementing Edge

      191
    • FIGURE 21-3: Timer1 Gate Enable Mode

      192
    • FIGURE 21-4: Timer1 Gate Toggle Mode

      192
    • FIGURE 21-5: Timer1 Gate Single-Pulse Mode

      193
    • FIGURE 21-6: Timer1 Gate Single-Pulse and Toggle Combined Mode

      194
  • 21.11 Timer1 Control Register

    195
    • Register 21-1: T1CON: Timer1 Control Register

      195
  • 21.12 Timer1 Gate Control Register

    196
    • Register 21-2: T1GCON: Timer1 Gate Control Register

      196
    • TABLE 21-5: Summary of Registers Associated with Timer1

      197
• 22.0 Timer2/4/6 Modules

  199
  • FIGURE 22-1: Timer2/4/6 Block Diagram

    199
  • 22.1 Timer2/4/6 Operation

    200
  • 22.2 Timer2/4/6 Interrupt

    200
  • 22.3 Timer2/4/6 Output

    200
  • 22.4 Timer2/4/6 Operation During Sleep

    200
  • 22.5 Timer2 Control Register

    201
    • Register 22-1: TxCON: Timer2/Timer4/Timer6 Control Register

      201
    • TABLE 22-1: Summary of Registers Associated With Timer2/4/6

      202
• 23.0 Data Signal Modulator

  203
  • FIGURE 23-1: Simplified Block Diagram of the Data Signal Modulator

    203
  • 23.1 DSM Operation

    204
  • 23.2 Modulator Signal Sources

    204
  • 23.3 Carrier Signal Sources

    204
  • 23.4 Carrier Synchronization

    204
    • FIGURE 23-2: ON OFF Keying (OOK) Synchronization

      205
    • EXAMPLE 23-1: No Synchronization (MDSHSYNC = 0, MDCLSYNC = 0)

      205
    • FIGURE 23-3: Carrier High Synchronization (MDSHSYNC = 1, MDCLSYNC = 0)

      205
    • FIGURE 23-4: Carrier Low Synchronization (MDSHSYNC = 0, MDCLSYNC = 1)

      206
    • FIGURE 23-5: Full Synchronization (MDSHSYNC = 1, MDCLSYNC = 1)

      206
  • 23.5 Carrier Source Polarity Select

    207
  • 23.6 Carrier Source Pin Disable

    207
  • 23.7 Programmable Modulator Data

    207
  • 23.8 Modulator Source Pin Disable

    207
  • 23.9 Modulated Output Polarity

    207
  • 23.10 Slew Rate Control

    207
  • 23.11 Operation in Sleep Mode

    207
  • 23.12 Effects of a Reset

    207
    • Register 23-1: MDCON: Modulation Control Register

      208
    • Register 23-2: MDSRC: Modulation Source Control Register

      209
    • Register 23-3: MDCARH: Modulation High Carrier Control Register

      210
    • Register 23-4: MDCARL: Modulation Low Carrier Control Register

      211
    • TABLE 23-1: Summary of Registers Associated with Data Signal Modulator Mode

      211
• 24.0 Capture/Compare/PWM Modules

  213
  • TABLE 24-1: PWM Resources

    213
  • 24.1 Capture Mode

    214
    • 24.1.1 CCP pin Configuration

      214
      • FIGURE 24-1: Capture Mode Operation Block Diagram

        214
    • 24.1.2 Timer1 Mode Resource

      214
    • 24.1.3 Software Interrupt Mode

      214
    • 24.1.4 CCP Prescaler

      214
      • EXAMPLE 24-1: Changing Between Capture Prescalers

        214
    • 24.1.5 Capture During Sleep

      215
    • 24.1.6 Alternate Pin Locations

      215
      • TABLE 24-2: Summary of Registers Associated with Capture

        215
  • 24.2 Compare Mode

    216
    • FIGURE 24-2: Compare Mode Operation Block Diagram

      216
    • 24.2.1 CCP Pin Configuration

      216
    • 24.2.2 Timer1 Mode Resource

      216
    • 24.2.3 Software Interrupt Mode

      216
    • 24.2.4 Special Event Trigger

      216
      • TABLE 24-3: Special Event Trigger

        216
    • 24.2.5 Compare During Sleep

      217
    • 24.2.6 Alternate Pin Locations

      217
      • TABLE 24-4: Summary of Registers Associated with Compare

        217
  • 24.3 PWM Overview

    218
    • 24.3.1 Standard PWM Operation

      218
      • FIGURE 24-3: CCP PWM Output Signal

        218
      • FIGURE 24-4: Simplified PWM Block Diagram

        218
    • 24.3.2 Setup for PWM Operation

      219
    • 24.3.3 Timer2/4/6 Timer Resource

      219
    • 24.3.4 PWM Period

      219
      • EQUATION 24-1: PWM Period

        219
    • 24.3.5 PWM Duty Cycle

      219
      • EQUATION 24-2: Pulse Width

        219
      • EQUATION 24-3: Duty Cycle Ratio

        219
    • 24.3.6 PWM Resolution

      220
      • EQUATION 24-4: PWM Resolution

        220
      • TABLE 24-5: Example PWM Frequencies and Resolutions (Fosc = 32 MHz)

        220
      • TABLE 24-6: Example PWM Frequencies and Resolutions (Fosc = 20 MHz)

        220
      • TABLE 24-7: Example PWM Frequencies and Resolutions (Fosc = 8 MHz)

        220
    • 24.3.7 Operation in Sleep Mode

      221
    • 24.3.8 Changes in System Clock Frequency

      221
    • 24.3.9 Effects of Reset

      221
    • 24.3.10 Alternate Pin Locations

      221
      • TABLE 24-8: Summary of Registers Associated with Standard PWM

        221
  • 24.4 PWM (Enhanced Mode)

    222
    • FIGURE 24-5: Example Simplified Block Diagram of the Enhanced PWM Mode

      222
    • TABLE 24-9: Example Pin Assignments for Various PWM Enhanced Modes

      223
    • FIGURE 24-6: Example PWM (Enhanced Mode) Output Relationships (Active-High State)

      223
    • FIGURE 24-7: Example Enhanced PWM Output Relationships (Active-Low State)

      224
    • 24.4.1 Half-Bridge Mode

      225
      • FIGURE 24-8: Example of Half- Bridge PWM Output

        225
      • FIGURE 24-9: Example of Half-Bridge Applications

        225
    • 24.4.2 Full-Bridge Mode

      226
      • FIGURE 24-10: Example of Full-Bridge Application

        226
      • FIGURE 24-11: Example of Full-Bridge PWM Output

        227
      • FIGURE 24-12: Example of PWM Direction Change

        228
      • FIGURE 24-13: Example of PWM Direction Change at Near 100% Duty Cycle

        229
    • 24.4.3 Enhanced PWM Auto- shutdown mode

      230
      • FIGURE 24-14: PWM Auto-shutdown With Firmware Restart (PxRSEN = 0)

        230
    • 24.4.4 Auto-restart Mode

      231
      • FIGURE 24-15: PWM Auto-shutdown With Auto-restart (PxRSEN = 1)

        231
    • 24.4.5 Programmable Dead-Band Delay Mode

      232
      • FIGURE 24-16: Example of Half- Bridge PWM Output

        232
      • FIGURE 24-17: Example of Half-Bridge Applications

        232
    • 24.4.6 PWM Steering Mode

      233
      • FIGURE 24-18: Simplified Steering Block Diagram

        233
    • 24.4.7 Start-up Considerations

      234
    • 24.4.8 Alternate Pin Locations

      234
      • FIGURE 24-19: Example of Steering Event at End of Instruction (STRxSYNC = 0)

        234
      • FIGURE 24-20: Example of Steering Event at Beginning of Instruction (STRxSYNC = 1)

        234
      • TABLE 24-10: Summary of Registers Associated with Enhanced PWM

        235
  • 24.5 CCP Control Registers

    236
    • Register 24-1: CCPXCON: CCPx Control Register

      236
    • Register 24-2: CCPTMRS: PWM Timer Selection Control Register 0

      237
    • Register 24-3: CCPxAS: CCPx Auto-shutdown Control Register

      238
    • Register 24-4: PWMxCON: Enhanced PWM Control Register

      239
    • Register 24-5: PSTRxCON: PWM Steering Control Register(1)

      240
• 25.0 Master Synchronous Serial Port (MSSP1 and MSSP2) Module

  241
  • 25.1 Master SSPx (MSSPx) Module Overview

    241
    • FIGURE 25-1: MSSPx Block Diagram (SPI mode)

      241
    • FIGURE 25-2: MSSPx Block Diagram (I2C™ Master mode)

      242
    • FIGURE 25-3: MSSPx Block Diagram (I2C™ Slave mode)

      243
  • 25.2 SPI Mode Overview

    244
    • FIGURE 25-4: SPI Master and Multiple Slave Connection

      245
    • 25.2.1 SPI Mode Registers

      245
    • 25.2.2 SPI Mode Operation

      245
      • FIGURE 25-5: SPI Master/Slave Connection

        246
    • 25.2.3 SPI Master Mode

      247
      • FIGURE 25-6: SPI Mode Waveform (Master Mode)

        247
    • 25.2.4 SPI Slave Mode

      248
    • 25.2.5 Slave Select Synchronization

      248
      • FIGURE 25-7: SPI Daisy-Chain Connection

        249
      • FIGURE 25-8: Slave Select Synchronous Waveform

        249
      • FIGURE 25-9: SPI Mode Waveform (Slave Mode With CKE = 0)

        250
      • FIGURE 25-10: SPI Mode Waveform (SLAve Mode With CKE = 1)

        250
    • 25.2.6 SPI Operation in Sleep Mode

      251
      • TABLE 25-1: Summary of Registers Associated with SPI Operation

        251
  • 25.3 I2C Mode Overview

    252
    • FIGURE 25-11: I2C Master/ Slave Connection

      252
    • 25.3.1 Clock Stretching

      253
    • 25.3.2 Arbitration

      253
  • 25.4 I2C Mode Operation

    254
    • 25.4.1 Byte Format

      254
    • 25.4.2 Definition of I2C Terminology

      254
    • 25.4.3 SDAx and SCLx Pins

      254
    • 25.4.4 SDAX Hold Time

      254
      • TABLE 25-2: I2C Bus Terms

        254
    • 25.4.5 Start Condition

      254
    • 25.4.6 Stop Condition

      255
    • 25.4.7 Restart Condition

      255
    • 25.4.8 Start/Stop Condition Interrupt Masking

      255
      • FIGURE 25-12: I2C START and STOP Conditions

        255
      • FIGURE 25-13: I2C Restart Condition

        255
    • 25.4.9 Acknowledge Sequence

      256
  • 25.5 I2C Slave Mode Operation

    256
    • 25.5.1 Slave Mode Addresses

      256
      • FIGURE 25-14: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0)

        258
      • FIGURE 25-15: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)

        259
      • FIGURE 25-16: I2C Slave, 7-Bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1)

        260
      • FIGURE 25-17: I2C Slave, 7-Bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1)

        261
    • 25.5.2 SLAVE Transmission

      262
      • FIGURE 25-18: I2C Slave, 7-Bit Address, Transmission (AHEN = 0)

        263
      • FIGURE 25-19: I2C Slave, 7-Bit Address, Transmission (AHEN = 1)

        265
    • 25.5.3 Slave mode 10-bit Address Reception

      266
    • 25.5.4 10-bit Addressing With Address Or Data Hold

      266
      • FIGURE 25-20: I2C Slave, 10-Bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0)

        267
      • FIGURE 25-21: I2C Slave, 10-Bit Address, Reception (SeN = 0, AHEN = 1, DHEN = 0)

        268
      • FIGURE 25-22: I2C Slave, 10-Bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0)

        269
    • 25.5.5 Clock Stretching

      270
    • 25.5.6 Clock Synchronization and the CKP bit

      270
      • FIGURE 25-23: Clock Synchronization Timing

        270
    • 25.5.7 General Call Address Support

      271
      • FIGURE 25-24: Slave Mode General Call Address Sequence

        271
    • 25.5.8 SSPx Mask Register

      271
  • 25.6 I2C Master Mode

    272
    • 25.6.1 I2C Master Mode Operation

      272
    • 25.6.2 Clock Arbitration

      273
      • FIGURE 25-25: Baud Rate Generator Timing with Clock Arbitration

        273
    • 25.6.3 WCOL Status Flag

      273
    • 25.6.4 I2C Master Mode Start Condition Timing

      274
      • FIGURE 25-26: First Start Bit Timing

        274
    • 25.6.5 I2C Master Mode Repeated Start Condition Timing

      275
      • FIGURE 25-27: Repeat Start Condition Waveform

        275
    • 25.6.6 I2C Master Mode Transmission

      276
      • FIGURE 25-28: I2C Master Mode Waveform (Transmission, 7 or 10-Bit Address)

        277
    • 25.6.7 I2C Master Mode Reception

      278
      • FIGURE 25-29: I2C Master Mode Waveform (Reception, 7-Bit Address)

        279
    • 25.6.8 Acknowledge Sequence Timing

      280
    • 25.6.9 Stop Condition Timing

      280
      • FIGURE 25-30: Acknowledge Sequence Waveform

        280
      • FIGURE 25-31: Stop Condition Receive or Transmit Mode

        280
    • 25.6.10 Sleep Operation

      281
    • 25.6.11 Effects of a Reset

      281
    • 25.6.12 Multi-Master Mode

      281
    • 25.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration

      281
      • FIGURE 25-32: Bus Collision Timing for Transmit and Acknowledge

        281
      • FIGURE 25-33: Bus Collision During Start Condition (SDAx Only)

        282
      • FIGURE 25-34: Bus Collision During Start Condition (SCLx = 0)

        283
      • FIGURE 25-35: BRG Reset Due to SDA Arbitration During Start Condition

        283
      • FIGURE 25-36: Bus Collision During a Repeated Start Condition (Case 1)

        284
      • FIGURE 25-37: Bus Collision During Repeated Start Condition (Case 2)

        284
      • FIGURE 25-38: Bus Collision During a Stop Condition (Case 1)

        285
      • FIGURE 25-39: Bus Collision During a Stop Condition (Case 2)

        285
      • TABLE 25-3: Summary of Registers Associated with I2C™ Operation

        286
  • 25.7 Baud Rate Generator

    287
    • FIGURE 25-40: Baud Rate Generator Block Diagram

      287
    • TABLE 25-4: MSSPx Clock Rate w/BRG

      287
    • Register 25-1: SSPxSTAT: SSPx STATUS Register

      288
    • Register 25-2: SSPxCON1: SSPx Control Register 1

      289
    • Register 25-3: SSPxCON2: SSPx Control Register 2

      290
    • Register 25-4: SSPxCON3: SSPx Control Register 3

      291
    • Register 25-5: SSPMSK: SSPx Mask Register

      292
    • Register 25-6: SSPxADD: MSSPx Address and Baud Rate Register (I2C Mode)

      292
• 26.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART)

  293
  • FIGURE 26-1: EUSART Transmit Block Diagram

    293
  • FIGURE 26-2: EUSART Receive Block Diagram

    294
  • 26.1 EUSART Asynchronous Mode

    295
    • 26.1.1 EUSART Asynchronous Transmitter

      295
      • FIGURE 26-3: Asynchronous Transmission

        296
      • FIGURE 26-4: Asynchronous Transmission (Back-to-Back)

        297
      • TABLE 26-1: Summary of Registers Associated with Asynchronous Transmission

        297
    • 26.1.2 EUSART Asynchronous Receiver

      298
      • FIGURE 26-5: Asynchronous Reception

        300
      • TABLE 26-2: Summary of Registers Associated with Asynchronous Reception

        301
  • 26.2 Clock Accuracy with Asynchronous Operation

    302
    • Register 26-1: TXSTA: Transmit Status and Control Register

      302
    • Register 26-2: RCSTA: Receive Status and Control Register (1)

      303
    • Register 26-3: BAUDCON: Baud Rate Control Register

      304
  • 26.3 EUSART Baud Rate Generator (BRG)

    305
    • EXAMPLE 26-1: Calculating Baud Rate Error

      305
    • TABLE 26-3: Baud Rate Formulas

      306
    • TABLE 26-4: Summary of Registers Associated with the Baud Rate Generator

      306
    • TABLE 26-5: BAUD Rates for Asynchronous Modes

      307
    • 26.3.1 Auto-Baud Detect

      310
      • TABLE 26-6: BRG Counter Clock Rates

        310
      • FIGURE 26-6: Automatic Baud Rate Calibration

        310
    • 26.3.2 Auto-baud Overflow

      311
    • 26.3.3 Auto-Wake-up on Break

      311
      • FIGURE 26-7: Auto-Wake-up Bit (WUE) Timing During Normal Operation

        312
      • FIGURE 26-8: Auto-Wake-up Bit (WUE) Timings During Sleep

        312
    • 26.3.4 BREAK Character Sequence

      313
    • 26.3.5 Receiving a Break Character

      313
      • FIGURE 26-9: Send Break Character Sequence

        313
  • 26.4 EUSART Synchronous Mode

    314
    • 26.4.1 Synchronous Master Mode

      314
      • FIGURE 26-10: Synchronous Transmission

        315
      • FIGURE 26-11: Synchronous Transmission (Through TXEN)

        315
      • TABLE 26-7: Summary of Registers Associated with Synchronous Master Transmission

        315
      • FIGURE 26-12: Synchronous Reception (Master Mode, SREN)

        317
      • TABLE 26-8: Summary of Registers Associated with Synchronous Master Reception

        317
    • 26.4.2 Synchronous Slave Mode

      318
      • TABLE 26-9: Summary of Registers Associated with Synchronous Slave Transmission

        318
      • TABLE 26-10: Summary of Registers Associated with Synchronous Slave Reception

        319
  • 26.5 EUSART Operation During Sleep

    320
    • 26.5.1 Synchronous Receive During Sleep

      320
    • 26.5.2 Synchronous Transmit During Sleep

      320
    • 26.5.3 Alternate Pin Locations

      320
• 27.0 Capacitive Sensing (CPS) Module

  321
  • FIGURE 27-1: Capacitive Sensing Block Diagram

    321
  • FIGURE 27-2: Capacitive Sensing Oscillator Block Diagram

    322
  • 27.1 Analog MUX

    323
  • 27.2 Capacitive Sensing Oscillator

    323
  • 27.3 Voltage References

    323
  • 27.4 Power Modes

    324
    • TABLE 27-1: Power Mode Selection

      324
  • 27.5 Timer Resources

    325
  • 27.6 Fixed Time Base

    325
    • 27.6.1 Timer0

      325
    • 27.6.2 Timer1

      325
      • TABLE 27-2: Timer1 Enable Function

        325
  • 27.7 Software Control

    325
    • 27.7.1 Nominal Frequency (No Capacitive Load)

      325
    • 27.7.2 Reduced Frequency (Additional Capacitive Load)

      325
    • 27.7.3 Frequency Threshold

      326
  • 27.8 Operation during Sleep

    326
    • Register 27-1: CPSCON0: Capacitive Sensing Control Register 0

      327
    • Register 27-2: CPSCON1: Capacitive Sensing Control Register 1

      328
    • TABLE 27-3: Summary of Registers Associated with Capacitive Sensing

      328
• 28.0 In-Circuit Serial Programming™ (ICSP™)

  329
  • 28.1 High-Voltage Programming Entry Mode

    329
    • FIGURE 28-1: Vpp Limiter Example Circuit

      329
  • 28.2 Low-Voltage Programming Entry Mode

    330
  • 28.3 Common Programming Interfaces

    330
    • FIGURE 28-2: ICD RJ-11 Style Connector Interface

      330
    • FIGURE 28-3: PICkit™ Style Connector Interface

      330
    • FIGURE 28-4: Typical Connection for ICSP™ Programming

      331
• 29.0 Instruction Set Summary

  333
  • 29.1 Read-Modify-Write Operations

    333
    • TABLE 29-1: Opcode Field Descriptions

      333
    • TABLE 29-2: Abbreviation Descriptions

      333
    • FIGURE 29-1: General Format for Instructions

      334
    • TABLE 29-3: PIC16(L)F1825/1829 Enhanced Instruction Set

      335
    • TABLE 29-3: PIC16(L)F1825/1829 Enhanced Instruction Set (Continued)

      336
  • 29.2 Instruction Descriptions

    337
• 30.0 Electrical Specifications

  347
  • Absolute Maximum Ratings(†)

    347
    • FIGURE 30-1: PIC16F1825/1829 Voltage Frequency Graph, -40°C £ Ta £ +125°C

      348
    • FIGURE 30-2: PIC16LF1825/1829 Voltage Frequency Graph, -40°C £ Ta £ +125°C

      348
    • FIGURE 30-3: HFINTOSC Frequency Accuracy Over Device Vdd and Temperature

      349
  • 30.1 DC Characteristics: PIC16(L)F1825/1829-I/E (Industrial, Extended)

    350
    • FIGURE 30-4: POR and POR Rearm with Slow Rising Vdd

      351
  • 30.2 DC Characteristics: PIC16(L)F1825/1829-I/E (Industrial, Extended)

    352
  • 30.3 DC Characteristics: PIC16(L)F1825/1829-I/E (Power-Down)

    355
  • 30.4 DC Characteristics: PIC16(L)F1825/1829-I/E

    357
  • 30.5 Memory Programming Requirements

    358
  • 30.6 Thermal Considerations

    359
  • 30.7 Timing Parameter Symbology

    360
    • FIGURE 30-5: Load Conditions

      360
  • 30.8 AC Characteristics: PIC16(L)F1825/1829-I/E

    361
    • FIGURE 30-6: Clock Timing

      361
    • TABLE 30-1: Clock Oscillator Timing Requirements

      361
    • TABLE 30-2: Oscillator Parameters

      362
    • TABLE 30-3: PLL Clock Timing Specifications (Vdd = 2.7V to 5.5V)

      362
    • FIGURE 30-7: CLKOUT and I/O Timing

      362
    • TABLE 30-4: CLKOUT and I/O Timing Parameters

      363
    • FIGURE 30-8: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing

      363
    • FIGURE 30-9: Brown-Out Reset Timing and Characteristics

      364
    • TABLE 30-5: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-Out Reset Parameters

      365
    • FIGURE 30-10: Timer0 and Timer1 External Clock Timings

      365
    • TABLE 30-6: Timer0 and Timer1 External Clock Requirements

      366
    • FIGURE 30-11: Capture/Compare/PWM Timings (CCP)

      366
    • TABLE 30-7: Capture/Compare/PWM Requirements (CCP)

      366
    • TABLE 30-8: PIC16(L)F1825/1829 A/D Converter (ADC) Characteristics(1,2,3)

      367
    • TABLE 30-9: PIC16(L)F1825/1829 A/D Conversion Requirements

      367
    • FIGURE 30-12: PIC16(L)F1825/1829 A/D Conversion Timing (Normal Mode)

      368
    • FIGURE 30-13: PIC16(L)F1825/1829 A/D Conversion Timing (Sleep Mode)

      368
    • TABLE 30-10: Comparator Specifications

      369
    • TABLE 30-11: Digital-to-Analog Converter (DAC) Specifications

      369
    • TABLE 30-12: PIC16(L)F1825/1829 Low Dropout (LDO) Regulator Characteristics:

      369
    • FIGURE 30-14: USART Synchronous Transmission (Master/Slave) Timing

      370
    • TABLE 30-13: USART Synchronous Transmission Requirements

      370
    • FIGURE 30-15: USART Synchronous Receive (Master/Slave) Timing

      370
    • TABLE 30-14: USART Synchronous Receive Requirements

      370
    • FIGURE 30-16: SPI Master Mode Timing (CKE = 0, SMP = 0)

      371
    • FIGURE 30-17: SPI Master Mode Timing (CKE = 1, SMP = 1)

      371
    • FIGURE 30-18: SPI Slave Mode Timing (CKE = 0)

      372
    • FIGURE 30-19: SPI Slave Mode Timing (CKE = 1)

      372
    • TABLE 30-15: SPI Mode Requirements

      373
    • FIGURE 30-20: I2C™ Bus Start/Stop Bits Timing

      374
    • TABLE 30-16: I2C™ Bus Start/Stop Bits Requirements

      374
    • FIGURE 30-21: I2C™ Bus Data Timing

      374
    • TABLE 30-17: I2C™ Bus Data Requirements

      375
    • TABLE 30-18: Cap Sense Oscillator Specifications

      376
    • FIGURE 30-22: Cap Sense Oscillator

      376
• 31.0 DC and AC Characteristics Graphs and Charts

  377
  • FIGURE 31-1: Idd, LP Oscillator Mode (Fosc = 32 kHz), PIC16LF1825/1829 only

    378
  • FIGURE 31-2: Idd, LP Oscillator Mode (Fosc = 32 kHz), PIC16F1825/1829 only

    378
  • FIGURE 31-3: Idd Typical, XT and EXTRC Oscillator, PIC16LF1825/1829 only

    379
  • FIGURE 31-4: Idd Maximum, XT and EXTRC Oscillator, PIC16LF1825/1829 only

    379
  • FIGURE 31-5: Idd Typical, XT and EXTRC Oscillator, PIC16F1825/1829 only

    380
  • FIGURE 31-6: Idd Maximum, XT and EXTRC Oscillator, PIC16F1825/1829 only

    380
  • FIGURE 31-7: Idd Typical, EC Oscillator, Medium-Power Mode, PIC16LF1825/1829 only

    381
  • FIGURE 31-8: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC16LF1825/1829 only

    381
  • FIGURE 31-9: Idd Typical, EC Oscillator, Medium-Power Mode, PIC16F1825/1829 only

    382
  • FIGURE 31-10: Idd Maximum, EC Oscillator, Medium-Power Mode, PIC16F1825/1829 only

    382
  • FIGURE 31-11: Idd, LFINTOSC Mode (Fosc = 31 kHz), PIC16LF1825/1829 only

    383
  • FIGURE 31-12: Idd, LFINTOSC Mode (Fosc = 31 kHz), PIC16F1825/1829 only

    383
  • FIGURE 31-13: Idd, MFINTOSC Mode (Fosc = 500 kHz), PIC16LF1825/1829 only

    384
  • FIGURE 31-14: Idd, MFINTOSC Mode (Fosc = 500 kHz), PIC16F1825/1829 only

    384
  • FIGURE 31-15: Idd Typical, HFINTOSC Mode, PIC16LF1825/1829 only

    385
  • FIGURE 31-16: Idd Maximum, HFINTOSC Mode, PIC16LF1825/1829 only

    385
  • FIGURE 31-17: Idd Typical, HFINTOSC Mode, PIC16F1825/1829 only

    386
  • FIGURE 31-18: Idd Maximum, HFINTOSC Mode, PIC16F1825/1829 only

    386
  • FIGURE 31-19: Idd, HS Oscillator, 32 MHz (8 MHz + 4xPLL), PIC16LF1825/1829 only

    387
  • FIGURE 31-20: Idd, HS Oscillator, 32 MHz (8 MHz + 4xPLL), PIC16F1825/1829 only

    387
  • FIGURE 31-21: Ipd Base, Low-Power Sleep Mode, PIC16LF1825/1829 Only

    388
  • FIGURE 31-22: Ipd Base, Low-Power Sleep Mode, PIC16F1825/1829 only

    388
  • FIGURE 31-23: Ipd, Watchdog Timer (WDT), PIC16LF1825/1829 only

    389
  • FIGURE 31-24: Ipd, Watchdog Timer (WDT), PIC16F1825/1829 only

    389
  • FIGURE 31-25: Ipd, Fixed Voltage Reference (FVR), PIC16LF1825/1829 only

    390
  • FIGURE 31-26: Ipd, Fixed Voltage Reference (FVR), PIC16F1825/1829 only

    390
  • FIGURE 31-27: Ipd, Brown-Out Reset (BOR), PIC16LF1825/1829 only

    391
  • FIGURE 31-28: Ipd, Brown-Out Reset (BOR), PIC16F1825/1829 only

    391
  • FIGURE 31-29: Ipd, Timer1 Oscillator (Fosc = 32 kHz), PIC16LF1825/1829 only

    392
  • FIGURE 31-30: Ipd, Timer1 Oscillator (Fosc = 32 kHz), PIC16F1825/1829 only

    392
  • FIGURE 31-31: Ipd, Capacitive Sensing (CPS) Module, Low-Current Range, CPSRM = 0, PIC16LF1825/1829 only

    393
  • FIGURE 31-32: Ipd, Capacitive Sensing (CPS) Module, Low-Current Range, CPSRM = 0, PIC16F1825/1829 only

    393
  • FIGURE 31-33: Ipd, Capacitive Sensing (CPS) Module, Medium-Current Range, CPSRM = 0, PIC16LF1825/1829 only

    394
  • FIGURE 31-34: Ipd, Capacitive Sensing (CPS) Module, Medium-Current Range, CPSRM = 0, PIC16F1825/1829 only

    394
  • FIGURE 31-35: Ipd, Capacitive Sensing (CPS) Module, High-Current Range, CPSRM = 0, PIC16LF1825/1829 only

    395
  • FIGURE 31-36: Ipd, Capacitive Sensing (CPS) Module, High-Current Range, CPSRM = 0, PIC16F1825/1829 only

    395
  • FIGURE 31-37: Ipd, Comparator, Low-Power Mode (CxSP = 0), PIC16LF1825/1829 only

    396
  • FIGURE 31-38: Ipd, Comparator, Low-Power Mode (CxSP = 0), PIC16F1825/1829 only

    396
  • FIGURE 31-39: Ipd, Comparator, Normal-Power Mode (CxSP = 1), PIC16LF1825/1829 only

    397
  • FIGURE 31-40: Ipd, Comparator, Normal-Power Mode (CxSP = 1), PIC16F1825/1829 only

    397
  • FIGURE 31-41: Voh vs. Ioh Over Temperature (Vdd = 5.0V), PIC16F1825/1829 only

    398
  • FIGURE 31-42: Vol vs. Iol Over Temperature (Vdd = 5.0V), PIC16F1825/1829 only

    398
  • FIGURE 31-43: Voh vs. Ioh Over Temperature (Vdd = 3.0V)

    399
  • FIGURE 31-44: Vol vs. Iol Over Temperature (Vdd = 3.0V)

    399
  • FIGURE 31-45: Voh vs. Ioh Over Temperature (Vdd = 1.8V)

    400
  • FIGURE 31-46: Vol vs. Iol Over Temperature (Vdd = 1.8V)

    400
  • FIGURE 31-47: POR Release Voltage

    401
  • FIGURE 31-48: POR Rearm Voltage, PIC16F1825/1829 Only

    401
  • FIGURE 31-49: Brown-out Reset Voltage, BORV = 1

    402
  • FIGURE 31-50: Brown-out Reset Hysteresis, BORV = 1

    402
  • FIGURE 31-51: Brown-out Reset Voltage, BORV = 0

    403
  • FIGURE 31-52: Brown-out Reset Hysteresis, BORV = 0

    403
  • FIGURE 31-53: WDT Time-out Period

    404
  • FIGURE 31-54: PWRT Period

    404
  • FIGURE 31-55: Comparator Hysteresis, Normal-Power Mode (CxSP = 1, CxHYS = 1)

    405
  • FIGURE 31-56: Comparator Hysteresis, Low-Power Mode (CxSP = 0, CxHYS = 1)

    405
  • FIGURE 31-57: Comparator Response Time, Normal-Power Mode (CxSP = 1)

    406
  • FIGURE 31-58: Comparator Response Time Over Temperature, Normal-Power Mode (CxSP = 1)

    406
  • FIGURE 31-59: Comparator Input Offset at 25°C, Normal-Power Mode (CxSP = 1), PIC16F1825/1829 Only

    407
• 32.0 Development Support

  409
  • 32.1 MPLAB Integrated Development Environment Software

    409
  • 32.2 MPLAB C Compilers for Various Device Families

    410
  • 32.3 HI-TECH C for Various Device Families

    410
  • 32.4 MPASM Assembler

    410
  • 32.5 MPLINK Object Linker/ MPLIB Object Librarian

    410
  • 32.6 MPLAB Assembler, Linker and Librarian for Various Device Families

    410
  • 32.7 MPLAB SIM Software Simulator

    411
  • 32.8 MPLAB REAL ICE In-Circuit Emulator System

    411
  • 32.9 MPLAB ICD 3 In-Circuit Debugger System

    411
  • 32.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express

    411
  • 32.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express

    412
  • 32.12 MPLAB PM3 Device Programmer

    412
  • 32.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits

    412
• 33.0 Packaging Information

  413
  • 33.1 Package Marking Information

    413
  • 33.1 Package Marking Information

    414
  • 33.1 Package Marking Information

    415
  • 33.1 Package Marking Information

    416
  • 33.2 Package Details

    417
• Appendix A: Data Sheet Revision History

  435
• Appendix B: Migrating From Other PIC® Devices

  435
  • TABLE B-1: Feature Comparison

    435
• INDEX

  437
  • A

    437
  • B

    437
  • C

    437
  • D

    438
  • E

    438
  • F

    439
  • I

    439
  • L

    439
  • M

    440
  • O

    440
  • P

    440
  • R

    440
  • S

    441
  • T

    442
  • U

    443
  • V

    443
  • W

    443
• The Microchip Web Site

  445
• Customer Change Notification Service

  445
• Customer Support

  445
• Reader Response

  446
• Product Identification System

  447
• Worldwide Sales

  448