Benutzerhandbuch für Microchip Technology MA330012

Inhaltsverzeichnis

• Operating Range:

  3
• High-Performance DSC CPU:

  3
• Direct Memory Access (DMA):

  3
• Interrupt Controller:

  3
• Digital I/O:

  3
• On-Chip Flash and SRAM:

  3
• System Management:

  3
• Power Management:

  3
• Timers/Capture/Compare/PWM:

  3
• Communication Modules:

  4
• Motor Control Peripherals:

  4
• Analog-to-Digital Converters (ADCs):

  4
• CMOS Flash Technology:

  4
• Packaging:

  4
• dsPIC33F Product Families

  5
  • dsPIC33F General Purpose Family Variants

    5
  • Pin Diagrams

    6
  • Pin Diagrams (Continued)

    7
  • Pin Diagrams (Continued)

    8
  • Pin Diagrams (Continued)

    9
  • Pin Diagrams (Continued)

    10
  • Pin Diagrams (Continued)

    11
  • Pin Diagrams (Continued)

    12
  • Pin Diagrams (Continued)

    13
  • dsPIC33F Motor Control Family Variants

    14
  • Pin Diagrams

    15
  • Pin Diagrams (Continued)

    16
  • Pin Diagrams (Continued)

    17
  • Pin Diagrams (Continued)

    18
  • Pin Diagrams (Continued)

    19
  • Pin Diagrams (Continued)

    20
  • Pin Diagrams (Continued)

    21
  • Table of Contents

    22
  • Most Current Data Sheet

    23
  • Errata

    23
  • Customer Notification System

    23
• 1.0 Device Overview

  25
  • FIGURE 1-1: dsPIC33F General Block Diagram

    26
  • TABLE 1-1: Pinout I/O Descriptions

    27
• 2.0 CPU

  29
  • 2.1 Data Addressing Overview

    29
  • 2.2 DSP Engine Overview

    29
  • 2.3 Special MCU Features

    29
    • FIGURE 2-1: dsPIC33F CPU Core Block Diagram

      30
    • FIGURE 2-2: dsPIC33F Programmer’s Model

      31
  • 2.4 CPU Control Registers

    32
    • Register 2-1: SR: CPU STATUS Register

      32
    • Register 2-2: CORCON: CORE Control Register

      34
  • 2.5 Arithmetic Logic Unit (ALU)

    35
    • 2.5.1 Multiplier

      35
    • 2.5.2 Divider

      35
  • 2.6 DSP Engine

    35
    • TABLE 2-1: DSP Instructions Summary

      35
    • FIGURE 2-3: DSP Engine Block Diagram

      36
    • 2.6.1 Multiplier

      37
    • 2.6.2 Data Accumulators and Adder/Subtracter

      37
    • 2.6.3 Barrel Shifter

      39
• 3.0 Memory Organization

  41
  • 3.1 Program Address Space

    41
    • FIGURE 3-1: Program Memory Map for dsPIC33F Family Devices

      41
    • 3.1.1 Program Memory Organization

      42
    • 3.1.2 Interrupt and Trap Vectors

      42
      • FIGURE 3-2: Program Memory Organization

        42
  • 3.2 Data Address Space

    43
    • 3.2.1 Data Space Width

      43
    • 3.2.2 Data Memory Organization and Alignment

      43
    • 3.2.3 SFR Space

      43
    • 3.2.4 Near Data Space

      43
      • FIGURE 3-3: Data Memory Map for dsPIC33F Devices with 8 Kbs RAM

        44
      • FIGURE 3-4: Data Memory Map for dsPIC33F Devices with 16 Kbs RAM

        45
      • FIGURE 3-5: Data Memory Map for dsPIC33F Devices with 30 Kbs RAM

        46
    • 3.2.5 X and Y Data Spaces

      47
    • 3.2.6 DMA RAM

      47
      • TABLE 3-1: CPU Core Registers Map

        48
      • TABLE 3-2: Change Notification Register Map

        49
      • TABLE 3-3: Interrupt Controller Register Map

        50
      • TABLE 3-4: Timer Register Map

        51
      • TABLE 3-5: Input Capture Register Map

        52
      • TABLE 3-6: Output Compare Register Map

        53
      • TABLE 3-7: 8-Output PWM Register Map

        54
      • TABLE 3-8: QEI Register Map

        55
      • TABLE 3-9: I2C1 Register Map

        55
      • TABLE 3-10: I2C2 Register Map

        55
      • TABLE 3-11: UART1 Register Map

        56
      • TABLE 3-12: UART2 Register Map

        56
      • TABLE 3-13: SPI1 Register Map

        56
      • TABLE 3-14: SPI2 Register Map

        56
      • TABLE 3-15: ADC1 Register Map

        57
      • TABLE 3-16: ADC2 Register Map

        57
      • TABLE 3-17: dma Register Map

        58
      • TABLE 3-18: ECAN1 Register Map When C1CTRL1.WIN = 0 or 1

        60
      • TABLE 3-19: ECAN1 Register Map When C1CTRL1.WIN = 0

        60
      • TABLE 3-20: ECAN1 Register Map When C1CTRL1.WIN = 1

        61
      • TABLE 3-21: ECAN2 Register Map When C2CTRL1.WIN = 0 or 1

        63
      • TABLE 3-22: ECAN2 Register Map When C2CTRL1.WIN = 0

        63
      • TABLE 3-23: ECAN2 Register Map When C2CTRL1.WIN = 1

        64
      • TABLE 3-24: DCI Register Map

        66
      • TABLE 3-25: PORTA Register Map(1)

        66
      • TABLE 3-26: PORTB Register Map(1)

        66
      • TABLE 3-27: PORTC Register Map(1)

        67
      • TABLE 3-28: PORTD Register Map(1)

        67
      • TABLE 3-29: PORTE Register Map(1)

        67
      • TABLE 3-30: PORTF Register Map(1)

        67
      • TABLE 3-31: PORTG Register Map(1)

        68
      • TABLE 3-32: System Control Register Map

        68
      • TABLE 3-33: NVM Register Map

        68
      • TABLE 3-34: PMD Register Map

        68
    • 3.2.7 Software Stack

      69
      • FIGURE 3-6: CALL Stack Frame

        69
    • 3.2.8 Data Ram Protection Feature

      69
  • 3.3 Instruction Addressing Modes

    69
    • 3.3.1 File Register Instructions

      69
    • 3.3.2 MCU Instructions

      69
      • TABLE 3-35: Fundamental Addressing Modes Supported

        70
    • 3.3.3 Move and Accumulator Instructions

      70
    • 3.3.4 MAC Instructions

      70
    • 3.3.5 Other Instructions

      70
  • 3.4 Modulo Addressing

    70
    • 3.4.1 Start and End Address

      71
    • 3.4.2 W Address Register Selection

      71
      • FIGURE 3-7: Modulo Addressing Operation Example

        71
    • 3.4.3 Modulo Addressing Applicability

      72
  • 3.5 Bit-Reversed Addressing

    72
    • 3.5.1 Bit-Reversed Addressing Implementation

      72
      • FIGURE 3-8: Bit-Reversed Address Example

        73
      • TABLE 3-36: Bit-Reversed Address Sequence (16-Entry)

        73
  • 3.6 Interfacing Program and Data Memory Spaces

    74
    • 3.6.1 Addressing Program Space

      74
      • TABLE 3-37: Program Space Address Construction

        74
      • FIGURE 3-9: Data Access from Program Space Address Generation

        75
    • 3.6.2 Data Access From Program Memory Using Table Instructions

      76
      • FIGURE 3-10: Accessing Program Memory with Table Instructions

        76
    • 3.6.3 Reading Data From Program Memory Using Program Space Visibility

      77
      • FIGURE 3-11: Program Space Visibility Operation

        77
• 4.0 Flash Program Memory

  79
  • 4.1 Table Instructions and Flash Programming

    79
    • FIGURE 4-1: Addressing for Table Registers

      79
  • 4.2 RTSP Operation

    80
  • 4.3 Control Registers

    80
  • 4.4 Programming Operations

    80
    • Register 4-1: NVMCON: Flash Memory Control Register

      81
    • 4.4.1 Programming Algorithm for Flash Program Memory

      82
      • EXAMPLE 4-1: Erasing a Program Memory Page

        82
      • EXAMPLE 4-2: Loading the Write Buffers

        83
      • EXAMPLE 4-3: Initiating a Programming Sequence

        83
• 5.0 Resets

  85
  • FIGURE 5-1: Reset System Block Diagram

    85
  • Register 5-1: RCON: Reset Control Register(1)

    86
  • TABLE 5-1: Reset Flag Bit Operation

    87
  • 5.1 Clock Source Selection at Reset

    87
    • TABLE 5-2: Oscillator Selection vs. Type of Reset (Clock Switching Enabled)

      87
  • 5.2 Device Reset Times

    87
    • TABLE 5-3: Reset Delay Times for Various Device Resets

      88
    • 5.2.1 POR and Long Oscillator Start-up Times

      88
    • 5.2.2 Fail-Safe Clock Monitor (FSCM) and Device Resets

      88
  • 5.3 Special Function Register Reset States

    88
• 6.0 Interrupt Controller

  89
  • 6.1 Interrupt Vector Table

    89
    • 6.1.1 Alternate Vector Table

      89
  • 6.2 Reset Sequence

    89
    • FIGURE 6-1: dsPIC33F Interrupt Vector Table

      90
    • TABLE 6-1: Interrupt Vectors

      91
    • TABLE 6-2: Trap Vectors

      92
  • 6.3 Interrupt Control and Status Registers

    93
    • Register 6-1: SR: CPU STATUS Register(1)

      94
    • Register 6-2: CORCON: CORE Control Register(1)

      94
    • Register 6-3: INTCON1: Interrupt Control Register 1

      95
    • Register 6-4: INTCON2: Interrupt Control Register 2

      97
    • Register 6-5: IFS0: Interrupt Flag Status Register 0

      98
    • Register 6-6: IFS1: Interrupt Flag Status Register 1

      100
    • Register 6-7: IFS2: Interrupt Flag Status Register 2

      102
    • Register 6-8: IFS3: Interrupt Flag Status Register 3

      104
    • Register 6-9: IFS4: Interrupt Flag Status Register 4

      106
    • Register 6-10: IEC0: Interrupt Enable Control Register 0

      107
    • Register 6-11: IEC1: Interrupt Enable Control Register 1

      109
    • Register 6-12: IEC2: Interrupt Enable Control Register 2

      111
    • Register 6-13: IEC3: Interrupt Enable Control Register 3

      113
    • Register 6-14: IEC4: Interrupt Enable Control Register 4

      115
    • Register 6-15: IPC0: Interrupt Priority Control Register 0

      116
    • Register 6-16: IPC1: Interrupt Priority Control Register 1

      117
    • Register 6-17: IPC2: Interrupt Priority Control Register 2

      118
    • Register 6-18: IPC3: Interrupt Priority Control Register 3

      119
    • Register 6-19: IPC4: Interrupt Priority Control Register 4

      120
    • Register 6-20: IPC5: Interrupt Priority Control Register 5

      121
    • Register 6-21: IPC6: Interrupt Priority Control Register 6

      122
    • Register 6-22: IPC7: Interrupt Priority Control Register 7

      123
    • Register 6-23: IPC8: Interrupt Priority Control Register 8

      124
    • Register 6-24: IPC9: Interrupt Priority Control Register 9

      125
    • Register 6-25: IPC10: Interrupt Priority Control Register 10

      126
    • Register 6-26: IPC11: Interrupt Priority Control Register 11

      127
    • Register 6-27: IPC12: Interrupt Priority Control Register 12

      128
    • Register 6-28: IPC13: Interrupt Priority Control Register 13

      129
    • Register 6-29: IPC14: Interrupt Priority Control Register 14

      130
    • Register 6-30: IPC15: Interrupt Priority Control Register 15

      131
    • Register 6-31: IPC16: Interrupt Priority Control Register 16

      132
    • Register 6-32: IPC17: Interrupt Priority Control Register 17

      133
    • Register 6-33: INTTREG: Interrupt Control and Status Register

      134
  • 6.4 Interrupt Setup Procedures

    135
    • 6.4.1 Initialization

      135
    • 6.4.2 Interrupt Service Routine

      135
    • 6.4.3 Trap Service Routine

      135
    • 6.4.4 Interrupt Disable

      135
• 7.0 Direct Memory Access (DMA)

  137
  • TABLE 7-1: Peripherals with DMA Support

    137
  • FIGURE 7-1: Top Level System Architecture Using a Dedicated Transaction Bus

    138
  • 7.1 DMAC Registers

    138
  • 7.2 DMAC Operating Modes

    138
    • 7.2.1 Byte or Word Transfer

      139
    • 7.2.2 Addressing Modes

      139
    • 7.2.3 DMA Transfer Direction

      139
    • 7.2.4 Null Data Peripheral Write Mode

      139
    • 7.2.5 Continuous or One-Shot Operation

      140
    • 7.2.6 ping-Pong Mode

      140
    • 7.2.7 Manual Transfer Mode

      140
    • 7.2.8 DMA Request Source Selection

      140
  • 7.3 DMA Interrupts and Traps

    140
  • 7.4 DMA Initialization Example

    141
    • EXAMPLE 7-1: DMA Sample Initialization Method

      141
    • Register 7-1: DMAxCON: DMA Channel x Control Register

      142
    • Register 7-2: DMAxREQ: DMA Channel x IRQ Select Register

      143
    • Register 7-3: DMAxSTA: DMA Channel x RAM Start Address Register A(1)

      144
    • Register 7-4: DMAxSTB: DMA Channel x RAM Start Address Register B(1)

      144
    • Register 7-5: DMAxPAD: DMA Channel x Peripheral Address Register(1)

      145
    • Register 7-6: DMAxCNT: DMA Channel x Transfer Count Register(1)

      145
    • Register 7-7: DMACS0: DMA Controller Status Register 0

      146
    • Register 7-8: DMACS1: DMA Controller Status Register 1

      148
    • Register 7-9: DSADR: Most Recent DMA RAM Address

      149
• 8.0 Oscillator Configuration

  151
  • FIGURE 8-1: dsPIC33F Oscillator System Diagram

    151
  • 8.1 CPU Clocking System

    152
    • 8.1.1 System Clock sources

      152
    • 8.1.2 System Clock Selection

      152
      • EQUATION 8-1: Device Operating Frequency

        152
    • 8.1.3 PLL Configuration

      152
      • EQUATION 8-2: Fosc Calculation

        152
      • EQUATION 8-3: XT with PLL Mode Example

        153
      • FIGURE 8-2: dsPIC33F PLL Block Diagram

        153
      • TABLE 8-1: Configuration Bit Values for Clock Selection

        153
      • Register 8-1: OSCCON: Oscillator Control Register

        154
      • Register 8-2: CLKDIV: Clock Divisor Register

        155
      • Register 8-3: PLLFBD: PLL Feedback Divisor Register

        156
      • Register 8-4: OSCTUN: FRC Oscillator Tuning Register

        157
  • 8.2 Clock Switching Operation

    158
    • 8.2.1 Enabling Clock Switching

      158
    • 8.2.2 Oscillator Switching Sequence

      158
  • 8.3 Fail-Safe Clock Monitor (FSCM)

    158
• 9.0 Power-Saving Features

  159
  • 9.1 Clock Frequency and Clock Switching

    159
  • 9.2 Instruction-Based Power-Saving Modes

    159
    • 9.2.1 Sleep Mode

      159
      • EXAMPLE 9-1: PWRSAV Instruction Syntax

        159
    • 9.2.2 Idle Mode

      160
    • 9.2.3 Interrupts Coincident with Power Save Instructions

      160
  • 9.3 Doze Mode

    160
  • 9.4 Peripheral Module Disable

    160
• 10.0 I/O Ports

  161
  • 10.1 Parallel I/O (PIO) Ports

    161
    • FIGURE 10-1: Block Diagram of a Typical Shared Port Structure

      161
  • 10.2 Open-Drain Configuration

    162
  • 10.3 Configuring Analog Port Pins

    162
  • 10.4 I/O Port Write/Read Timing

    162
  • 10.5 Input Change Notification

    162
    • EXAMPLE 10-1: Port Write/Read Example

      162
• 11.0 Timer1

  163
  • FIGURE 11-1: 16-bit Timer1 Module Block Diagram

    163
  • Register 11-1: T1CON: Timer1 Control Register

    164
• 12.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9

  165
  • FIGURE 12-1: Timer2/3 (32-bit) Block Diagram(1)

    166
  • FIGURE 12-2: Timer2 (16-bit) Block Diagram

    167
  • Register 12-1: TxCON (T2CON, T4CON, T6CON or T8CON) Control Register

    168
  • Register 12-2: TyCON (T3CON, T5CON, T7CON or T9CON) Control Register

    169
• 13.0 Input Capture

  171
  • FIGURE 13-1: Input Capture Block Diagram

    171
  • 13.1 Input Capture Registers

    172
    • Register 13-1: ICxCON: Input Capture x Control Register

      172
• 14.0 Output Compare

  173
  • 14.1 Setup for Single Output Pulse Generation

    173
  • 14.2 Setup for Continuous Output Pulse Generation

    173
  • 14.3 Pulse-Width Modulation Mode

    174
    • 14.3.1 PWM Period

      174
      • EQUATION 14-1: Calculating the PWM Period

        174
    • 14.3.2 PWM Duty Cycle

      174
      • EQUATION 14-2: Calculation for Maximum PWM Resolution

        174
      • EXAMPLE 14-1: PWM Period and Duty Cycle Calculations

        174
      • TABLE 14-1: Example PWM Frequencies and Resolutions at 4 MIPS (Fcy = 4 MHz)

        175
      • TABLE 14-2: Example PWM Frequencies and Resolutions at 16 MIPS (Fcy = 16 MHz)

        175
      • TABLE 14-3: Example PWM Frequencies and Resolutions at 40 MIPS (Fcy = 40 MHz)

        175
      • FIGURE 14-1: Output Compare Module Block Diagram

        175
  • 14.4 Output Compare Register

    176
    • Register 14-1: OCxCON: Output Compare x Control Register

      176
• 15.0 Motor Control PWM Module

  177
  • FIGURE 15-1: PWM Module Block Diagram

    178
  • 15.1 PWM Time Base

    179
    • 15.1.1 Free-Running Mode

      179
    • 15.1.2 Single-Shot Mode

      179
    • 15.1.3 Continuous Up/Down Count Modes

      179
    • 15.1.4 Double Update Mode

      180
    • 15.1.5 PWM Time Base Prescaler

      180
    • 15.1.6 PWM Time Base Postscaler

      180
  • 15.2 PWM Period

    180
    • EQUATION 15-1: PWM Period

      180
    • EQUATION 15-2: PWM Resolution

      180
  • 15.3 Edge-Aligned PWM

    180
    • FIGURE 15-2: Edge-Aligned PWM

      180
  • 15.4 Center-Aligned PWM

    181
    • FIGURE 15-3: Center-Aligned PWM

      181
  • 15.5 PWM Duty Cycle Comparison Units

    181
    • 15.5.1 Duty Cycle Register Buffers

      181
    • 15.5.2 Duty Cycle Immediate Updates

      181
  • 15.6 Complementary PWM Operation

    182
  • 15.7 Dead-Time Generators

    182
    • 15.7.1 Dead-Time Generators

      182
      • FIGURE 15-4: Dead-Time Timing Diagram

        182
    • 15.7.2 Dead-Time Assignment

      183
      • TABLE 15-1: Dead-Time Selection Bits

        183
    • 15.7.3 Dead-Time Ranges

      183
  • 15.8 Independent PWM Output

    183
  • 15.9 Single Pulse PWM Operation

    183
  • 15.10 PWM Output Override

    183
    • 15.10.1 Complementary Output Mode

      183
    • 15.10.2 Override Synchronization

      184
  • 15.11 PWM Output and Polarity Control

    184
    • 15.11.1 Output Pin Control

      184
  • 15.12 PWM Fault Pins

    184
    • 15.12.1 Fault Pin Enable Bits

      184
    • 15.12.2 Fault States

      184
    • 15.12.3 Fault Pin Priority

      184
    • 15.12.4 Fault Input Modes

      185
  • 15.13 PWM Update Lockout

    185
  • 15.14 PWM Special Event Trigger

    185
    • 15.14.1 Special Event Trigger Postscaler

      185
  • 15.15 PWM Operation During CPU Sleep Mode

    185
  • 15.16 PWM Operation During CPU Idle Mode

    185
    • Register 15-1: PTCON: PWM Time Base Control Register

      186
    • Register 15-2: PTMR: PWM Timer Count Value Register

      187
    • Register 15-3: PTPER: PWM Time Base Period Register

      187
    • Register 15-4: SEVTCMP: Special Event Compare Register

      188
    • Register 15-5: PWMCON1: PWM Control Register 1

      189
    • Register 15-6: PWMCON2: PWM Control Register 2

      190
    • Register 15-7: DTCON1: Dead-Time Control Register 1

      191
    • Register 15-8: DTCON2: Dead-Time Control Register 2

      192
    • Register 15-9: FLTACON: Fault A Control Register

      193
    • Register 15-10: FLTBCON: Fault B Control Register

      194
    • Register 15-11: OVDCON: Override Control Register

      195
    • Register 15-12: PDC1: PWM Duty Cycle Register 1

      196
    • Register 15-13: PDC2: PWM Duty Cycle Register 2

      196
    • Register 15-14: PDC3: PWM Duty Cycle Register 3

      197
    • Register 15-15: PDC4: PWM Duty Cycle Register 4

      197
• 16.0 Quadrature Encoder Interface (QEI) Module

  199
  • FIGURE 16-1: Quadrature Encoder Interface Block Diagram

    199
  • 16.1 Quadrature Encoder Interface Logic

    200
  • 16.2 16-bit Up/Down Position Counter Mode

    200
    • 16.2.1 Position Counter Error Checking

      200
    • 16.2.2 Position Counter Reset

      200
    • 16.2.3 Count Direction Status

      200
  • 16.3 Position Measurement Mode

    200
  • 16.4 Programmable Digital Noise Filters

    201
  • 16.5 Alternate 16-bit Timer/Counter

    201
  • 16.6 QEI Module Operation During CPU Sleep Mode

    201
    • 16.6.1 QEI Operation During CPU Sleep Mode

      201
    • 16.6.2 Timer Operation During CPU Sleep Mode

      201
  • 16.7 QEI Module Operation During CPU Idle Mode

    201
    • 16.7.1 QEI Operation During CPU Idle Mode

      201
    • 16.7.2 Timer Operation During CPU Idle Mode

      202
  • 16.8 Quadrature Encoder Interface Interrupts

    202
  • 16.9 Control and Status Registers

    202
    • Register 16-1: QEICON: QEI Control Register 

      203
    • Register 16-2: DFLTCON: Digital Filter Control Register 

      205
• 17.0 Serial Peripheral Interface (SPI)

  207
  • FIGURE 17-1: SPI Module Block Diagram

    208
  • FIGURE 17-2: SPI Master/Slave Connection

    209
  • FIGURE 17-3: SPI Master, Frame Master Connection Diagram

    209
  • FIGURE 17-4: SPI Master, Frame Slave Connection Diagram

    209
  • FIGURE 17-5: SPI Slave, Frame Master Connection Diagram

    210
  • FIGURE 17-6: SPI Slave, Frame Slave Connection Diagram

    210
  • EQUATION 17-1: Relationship Between Device and SPI Clock Speed

    210
  • TABLE 17-1: Sample SCKx Frequencies

    210
  • Register 17-1: SPIxSTAT: SPIx Status and Control Register

    211
  • Register 17-2: SPIxCON1: SPIx Control Register 1

    212
  • Register 17-3: SPIxCON2: SPIx Control Register 2

    213
• 18.0 Inter-Integrated Circuit (I2C)

  215
  • 18.1 Operating Modes

    215
  • 18.2 I2C Registers

    215
  • 18.3 I2C Interrupts

    215
  • 18.4 Baud Rate Generator

    215
    • FIGURE 18-1: I2C™ Block Diagram (x = 1 or 2)

      216
  • 18.5 I2C Module Addresses

    217
    • TABLE 18-1: 7-bit I2C™ Slave Addresses supported by dsPIC33F

      217
  • 18.6 Slave Address Masking

    217
  • 18.7 IPMI Support

    217
  • 18.8 General Call Address Support

    217
  • 18.9 Automatic Clock Stretch

    217
    • 18.9.1 Transmit Clock Stretching

      217
    • 18.9.2 Receive Clock Stretching

      217
  • 18.10 Software Controlled Clock Stretching (STREN = 1)

    217
  • 18.11 Slope Control

    218
  • 18.12 Clock Arbitration

    218
  • 18.13 Multi-Master Communication, Bus Collision and Bus Arbitration

    218
    • Register 18-1: I2CxCON: I2Cx Control Register

      219
    • Register 18-2: I2CxSTAT: I2Cx Status Register

      221
    • Register 18-3: I2CxMSK: I2Cx Slave Mode Address Mask Register

      223
• 19.0 Universal Asynchronous Receiver Transmitter (UART)

  225
  • FIGURE 19-1: UART Simplified Block Diagram

    225
  • 19.1 UART Baud Rate Generator (BRG)

    226
    • EQUATION 19-1: UART Baud Rate With BRGH = 0

      226
    • EQUATION 19-2: UART Baud Rate With BRGH = 1

      226
    • EXAMPLE 19-1: Baud Rate Error Calculation (BRGH = 0)

      226
  • 19.2 Transmitting in 8-bit Data Mode

    227
  • 19.3 Transmitting in 9-bit Data Mode

    227
  • 19.4 Break and Sync Transmit Sequence

    227
  • 19.5 Receiving in 8-bit or 9-bit Data Mode

    227
  • 19.6 Flow Control Using UxCTS and UxRTS Pins

    227
  • 19.7 Infrared Support

    227
    • 19.7.1 External IrDA Support – IrDA Clock Output

      227
    • 19.7.2 Built-in IrDA Encoder and Decoder

      227
      • Register 19-1: UxMODE: UARTx Mode Register

        228
      • Register 19-2: UxSTA: UARTx Status and Control Register

        230
• 20.0 Enhanced CAN Module

  233
  • 20.1 Overview

    233
  • 20.2 Frame Types

    233
    • FIGURE 20-1: ECAN™ Module Block Diagram

      234
  • 20.3 Modes of Operation

    235
    • 20.3.1 Initialization Mode

      235
    • 20.3.2 Disable Mode

      235
    • 20.3.3 Normal Operation Mode

      235
    • 20.3.4 Listen Only Mode

      235
    • 20.3.5 Listen All Messages Mode

      235
    • 20.3.6 Loopback Mode

      235
  • 20.4 Message Reception

    235
    • 20.4.1 Receive Buffers

      235
    • 20.4.2 FIFO Buffer Mode

      236
    • 20.4.3 Message Acceptance Filters

      236
    • 20.4.4 Message Acceptance Filter Masks

      236
    • 20.4.5 Receive Errors

      236
    • 20.4.6 Receive Interrupts

      236
  • 20.5 Message Transmission

    237
    • 20.5.1 Transmit Buffers

      237
    • 20.5.2 Transmit Message Priority

      237
    • 20.5.3 Transmission Sequence

      237
    • 20.5.4 Automatic Processing of Remote Transmission Requests

      237
    • 20.5.5 Aborting Message Transmission

      237
    • 20.5.6 Transmission Errors

      237
    • 20.5.7 Transmit Interrupts

      238
  • 20.6 Baud Rate Setting

    238
    • 20.6.1 Bit Timing

      238
      • FIGURE 20-2: ECAN™ Module Bit Timing

        238
    • 20.6.2 Prescaler Setting

      239
      • EQUATION 20-1: Time Quantum for Clock Generation

        239
    • 20.6.3 Propagation Segment

      239
    • 20.6.4 Phase Segments

      239
    • 20.6.5 Sample Point

      239
    • 20.6.6 Synchronization

      239
      • Register 20-1: CiCTRL1: eCAN Control Register 1

        240
      • Register 20-2: CiCTRL2: eCAN Control Register 2

        241
      • Register 20-3: CiVEC: eCAN Interrupt Code Register

        242
      • Register 20-4: CiFCTRL: eCAN FIFO Control Register

        243
      • Register 20-5: CiFIFO: eCAN FIFO Status Register

        244
      • Register 20-6: CiINTF: eCAN Interrupt Flag Register

        245
      • Register 20-7: CiINTE: eCAN Interrupt Enable Register

        246
      • Register 20-8: CiEC: eCAN Transmit/Receive Error Count Register

        247
      • Register 20-9: CiCFG1: eCAN Baud Rate Configuration Register 1

        248
      • Register 20-10: CiCFG2: eCAN Baud Rate Configuration Register 2

        249
      • Register 20-11: CiFEN1: ECAN Acceptance Filter Enable Register

        250
      • Register 20-12: CiBUFPNT1: ECAN Filter 0-3 Buffer Pointer Register

        250
      • Register 20-13: CiBUFPNT2: ECAN Filter 4-7 Buffer Pointer Register

        251
      • Register 20-14: CiBUFPNT3: ECAN Filter 8-11 Buffer Pointer Register

        251
      • Register 20-15: CiBUFPNT4: ECAN Filter 12-15 Buffer Pointer Register

        252
      • Register 20-16: CiRXFnSID: ECAN Acceptance Filter n Standard Identifier (n = 0, 1, ..., 15)

        253
      • Register 20-17: CiRXFnEID: ECAN Acceptance Filter n Extended Identifier (n = 0, 1, ..., 15)

        253
      • Register 20-18: CiFMSKSEL1: ECAN Filter 7-0 Mask Selection Register

        254
      • Register 20-19: CiRXMnSID: ECAN Acceptance Filter Mask n Standard Identifier

        255
      • Register 20-20: CiRXMnEID: ECAN Acceptance Filter Mask n Extended Identifier

        255
      • Register 20-21: CiRXFUL1: ECAN Receive Buffer Full Register 1

        256
      • Register 20-22: CiRXFUL2: ECAN Receive Buffer Full Register 2

        256
      • Register 20-23: CiRXOVF1: ECAN Receive Buffer Overflow Register 1

        257
      • Register 20-24: CiRXOVF2: ECAN Receive Buffer Overflow Register 2

        257
      • Register 20-25: CiTRmnCON: ECAN TX/RX Buffer m Control Register (m = 0,2,4,6; n = 1,3,5,7)

        258
      • Register 20-26: CiTRBnSID: ECAN Buffer n Standard Identifier (n = 0, 1, ..., 31)

        259
      • Register 20-27: CiTRBnEID: ECAN Buffer n Extended Identifier (n = 0, 1, ..., 31)

        259
      • Register 20-28: CiTRBnDLC: ECAN Buffer n Data Length Control (n = 0, 1, ..., 31)

        260
      • Register 20-29: CiTRBnDm: ECAN Buffer n Data Field Byte m (n = 0, 1, ..., 31; m = 0, 1, ..., 7)(1)

        260
      • Register 20-30: CiTRBnSTAT: ECAN Receive Buffer n Status (n = 0, 1, ..., 31)

        261
• 21.0 Data Converter Interface (DCI) Module

  263
  • 21.1 Module Introduction

    263
  • 21.2 Module I/O Pins

    263
    • 21.2.1 CSCK Pin

      263
    • 21.2.2 CSDO Pin

      263
    • 21.2.3 CSDI Pin

      263
    • 21.2.4 Buffer Data Alignment

      263
    • 21.2.5 Transmit/Receive Shift Register

      263
    • 21.2.6 DCI Buffer Control

      263
      • FIGURE 21-1: DCI Module Block Diagram

        264
  • 21.3 DCI Module Operation

    265
    • 21.3.1 Module Enable

      265
    • 21.3.2 Word Size Selection Bits

      265
    • 21.3.3 Frame Sync Generator

      265
      • EQUATION 21-1: COFSG Period

        265
    • 21.3.4 Frame Sync Mode Control Bits

      265
    • 21.3.5 Master Frame Sync Operation

      265
    • 21.3.6 Slave Frame Sync Operation

      266
      • FIGURE 21-2: Frame Sync Timing, Multi-Channel Mode

        266
      • FIGURE 21-3: Frame Sync Timing, AC-Link Start-Of-Frame

        266
      • FIGURE 21-4: I2S Interface Frame Sync Timing

        266
    • 21.3.7 Bit Clock Generator

      267
      • EQUATION 21-2: Bit Clock Frequency

        267
      • TABLE 21-1: Device Frequencies for Common Codec CSCK Frequencies

        267
    • 21.3.8 Sample Clock Edge Control Bit

      268
    • 21.3.9 Data Justification Control Bit

      268
    • 21.3.10 Transmit Slot Enable Bits

      268
    • 21.3.11 Receive Slot Enable Bits

      268
    • 21.3.12 Slot Enable Bits Operation with Frame SynC

      268
    • 21.3.13 Synchronous Data Transfers

      268
    • 21.3.14 Buffer Length Control

      269
    • 21.3.15 Buffer Alignment With Data Frames

      269
    • 21.3.16 Transmit STATUS BITS

      269
    • 21.3.17 RECEIVE STATUS bits

      269
    • 21.3.18 SLOT Status Bits

      270
    • 21.3.19 CSDO Mode Bit

      270
    • 21.3.20 Digital Loopback mode

      270
    • 21.3.21 Underflow Mode Control Bit

      270
  • 21.4 DCI Module Interrupts

    270
  • 21.5 DCI Module Operation During CPU Sleep and Idle Modes

    270
    • 21.5.1 DCI Module Operation During CPU Sleep Mode

      270
    • 21.5.2 DCI Module Operation During CPU Idle Mode

      270
  • 21.6 AC-Link Mode Operation

    270
    • 21.6.1 16-bit AC-link Mode

      270
    • 21.6.2 20-bit AC-Link Mode

      271
  • 21.7 I2S Mode Operation

    271
    • 21.7.1 I2S Frame and data word Length Selection

      271
    • 21.7.2 I2S DATA Justification

      271
      • Register 21-1: DCICON1: DCI Control Register 1

        272
      • Register 21-2: DCICON2: DCI Control Register 2

        273
      • Register 21-3: DCICON3: DCI Control Register 3

        274
      • Register 21-4: DCISTAT: DCI Status Register

        275
      • Register 21-5: RSCON: DCI Receive Slot Control Register

        276
      • Register 21-6: TSCON: DCI Transmit Slot Control Register

        276
• 22.0 10-bit/12-bit Analog-to-Digital Converter (ADC)

  277
  • 22.1 Key Features

    277
  • 22.2 ADC Initialization

    277
  • 22.3 ADC and DMA

    277
    • FIGURE 22-1: ADC1 Module Block Diagram

      278
    • FIGURE 22-2: ADC2 Module Block Diagram(1)

      279
    • EQUATION 22-1: ADC Conversion Clock Period

      280
    • FIGURE 22-3: ADC Transfer Function (10-bit Example)

      280
    • FIGURE 22-4: ADC Conversion Clock Period Block Diagram

      280
    • Register 22-1: ADxCON1: ADCx control register 1(where x = 1 or 2)

      281
    • Register 22-2: ADxCON2: ADCx control register 2 (where x = 1 or 2)

      283
    • Register 22-3: ADxCON3: ADCx Control Register 3

      285
    • Register 22-4: ADxCON4: ADCx Control Register 4

      286
    • Register 22-5: ADxCHS123: ADCx INPUT Channel 1, 2, 3 select Register

      287
    • Register 22-6: ADxCHS0: ADCx INPUT Channel 0 select Register

      288
    • Register 22-7: ADxCSSH: ADCx INPUT SCAN SELECT register High(1)

      289
    • Register 22-8: ADxCSSL: ADCx INPUT SCAN SELECT register Low(1)

      289
    • Register 22-9: AD1PCFGH: ADC1 Port configuration register hIGH(1,2)

      290
    • Register 22-10: ADxPCFGL: ADCx Port configuration register Low(1,2)

      290
• 23.0 Special Features

  291
  • 23.1 Configuration Bits

    291
    • TABLE 23-1: Device Configuration Register Map

      291
    • TABLE 23-2: dsPIC33F Configuration Bits Description

      292
  • 23.2 On-Chip Voltage Regulator

    295
    • FIGURE 23-1: Connections for the On-Chip Voltage Regulator(1)

      295
  • 23.3 Watchdog Timer (WDT)

    296
    • FIGURE 23-2: WDT Block Diagram

      296
  • 23.4 JTAG Interface

    297
  • 23.5 Code Protection and CodeGuard™ Security

    297
  • 23.6 In-Circuit Serial Programming

    297
  • 23.7 In-Circuit Debugger

    297
• 24.0 Instruction Set Summary

  299
  • TABLE 24-1: Symbols used in Opcode Descriptions

    300
  • TABLE 24-2: Instruction Set OVERVIEW

    302
• 25.0 Development Support

  307
  • 25.1 MPLAB Integrated Development Environment Software

    307
  • 25.2 MPASM Assembler

    308
  • 25.3 MPLAB C18 and MPLAB C30 C Compilers

    308
  • 25.4 MPLINK Object Linker/ MPLIB Object Librarian

    308
  • 25.5 MPLAB ASM30 Assembler, Linker and Librarian

    308
  • 25.6 MPLAB SIM Software Simulator

    308
  • 25.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator

    309
  • 25.8 MPLAB ICE 4000 High-Performance In-Circuit Emulator

    309
  • 25.9 MPLAB ICD 2 In-Circuit Debugger

    309
  • 25.10 MPLAB PM3 Device Programmer

    309
  • 25.11 PICSTART Plus Development Programmer

    310
  • 25.12 PICkit 2 Development Programmer

    310
  • 25.13 Demonstration, Development and Evaluation Boards

    310
• 26.0 Electrical Characteristics

  311
  • Absolute Maximum Ratings(Note 1)

    311
  • 26.1 DC Characteristics

    312
    • TABLE 26-1: Operating MIPS vs. Voltage

      312
    • TABLE 26-2: Thermal Operating Conditions

      312
    • TABLE 26-3: Thermal Packaging Characteristics

      312
    • TABLE 26-4: DC Temperature and Voltage specifications

      312
    • TABLE 26-5: DC Characteristics: Operating Current (Idd) 

      313
    • TABLE 26-6: DC Characteristics: Idle Current (iidle)

      314
    • TABLE 26-7: DC Characteristics: Power-Down Current (Ipd)

      314
    • TABLE 26-8: DC Characteristics: doze Current (Idoze)

      315
    • TABLE 26-9: DC Characteristics: I/O Pin Input Specifications

      316
    • TABLE 26-10: DC Characteristics: I/O Pin Output Specifications

      317
    • TABLE 26-11: DC Characteristics: Program Memory

      317
    • TABLE 26-12: Internal Voltage Regulator Specifications

      317
  • 26.2 AC Characteristics and Timing Parameters

    318
    • TABLE 26-13: Temperature and Voltage Specifications – AC

      318
    • FIGURE 26-1: Load Conditions for Device Timing Specifications

      318
    • TABLE 26-14: cAPAcITIVE lOADING rEQUIREMENTS ON oUTPUT pINS

      318
    • FIGURE 26-2: External Clock Timing

      319
    • TABLE 26-15: External Clock Timing Requirements

      319
    • TABLE 26-16: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)

      320
    • TABLE 26-17: AC Characteristics: Internal RC Accuracy

      320
    • TABLE 26-18: Internal RC accuracy

      320
    • FIGURE 26-3: CLKO and I/O Timing Characteristics

      321
    • TABLE 26-19: CLKO and I/O Timing Requirements

      321
    • FIGURE 26-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Character...

      322
    • TABLE 26-20: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset...

      323
    • FIGURE 26-5: Timer1, 2, 3, 4, 5, 6, 7, 8 and 9 External Clock Timing Characteristics

      324
    • TABLE 26-21: Timer1 External Clock Timing Requirements(1)

      324
    • TABLE 26-22: Timer2, Timer4, Timer6 and Timer8 External Clock Timing Requirements

      325
    • TABLE 26-23: Timer3, Timer5, Timer7 and Timer9 External Clock Timing Requirements

      325
    • FIGURE 26-6: TimerQ (QEI Module) External Clock Timing Characteristics

      326
    • TABLE 26-24: QEI module External Clock Timing Requirements

      326
    • FIGURE 26-7: INPUT CAPTURE (CAPx) TIMING Characteristics

      327
    • TABLE 26-25: Input Capture timing requirements

      327
    • FIGURE 26-8: Output Compare Module (OCx) Timing Characteristics

      327
    • TABLE 26-26: Output Compare Module timing requirements

      327
    • FIGURE 26-9: OC/PWM Module Timing Characteristics

      328
    • TABLE 26-27: Simple OC/PWM MODE Timing Requirements

      328
    • FIGURE 26-10: Motor Control PWM Module fault Timing Characteristics

      329
    • FIGURE 26-11: Motor Control PWM Module Timing Characteristics

      329
    • TABLE 26-28: Motor Control PWM Module Timing Requirements

      329
    • FIGURE 26-12: QEA/QEB Input Characteristics

      330
    • TABLE 26-29: Quadrature Decoder Timing Requirements

      330
    • FIGURE 26-13: QEI Module Index Pulse Timing Characteristics

      331
    • TABLE 26-30: QEI INDEX PULSE Timing Requirements

      331
    • FIGURE 26-14: SPIx Module Master Mode (CKE = 0) Timing Characteristics

      332
    • TABLE 26-31: SPIx Master mode (cke = 0) Timing requirements

      332
    • FIGURE 26-15: SPIx Module Master Mode (CKE = 1) Timing Characteristics

      333
    • TABLE 26-32: SPIx Module Master mode (cke = 1) Timing requirements

      333
    • FIGURE 26-16: SPIx Module Slave Mode (CKE = 0) Timing Characteristics

      334
    • TABLE 26-33: SPIx Module Slave mode (cke = 0) Timing requirements

      334
    • FIGURE 26-17: SPIx Module Slave Mode (CKE = 1) Timing Characteristics

      335
    • TABLE 26-34: SPIx Module Slave mode (cke = 1) Timing requirements 

      336
    • FIGURE 26-18: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)

      337
    • FIGURE 26-19: I2Cx Bus Data Timing Characteristics (Master mode)

      337
    • TABLE 26-35: I2Cx Bus Data Timing Requirements (Master Mode)

      338
    • FIGURE 26-20: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)

      339
    • FIGURE 26-21: I2Cx Bus Data Timing Characteristics (slave mode)

      339
    • TABLE 26-36: I2Cx Bus Data Timing Requirements (Slave Mode)

      340
    • FIGURE 26-22: DCI Module (Multi-channel, I2S modes) Timing Characteristics

      341
    • TABLE 26-37: DCI Module (Multi-channel, I2S modes) Timing Requirements

      342
    • FIGURE 26-23: DCI Module (AC-link mode) Timing Characteristics

      343
    • TABLE 26-38: DCI Module (AC-Link Mode) Timing Requirements

      344
    • FIGURE 26-24: CAN Module I/O Timing Characteristics

      345
    • TABLE 26-39: CAN Module I/O Timing Requirements

      345
    • TABLE 26-40: ADC Module Specifications

      345
    • FIGURE 26-25: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, as...

      348
    • FIGURE 26-26: ADC Conversion (10-bit mode) Timing cHARACTERISTICS (chps<1:0> = 01, SIMSAM = 0, as...

      349
    • TABLE 26-41: ADC CONVERSION (10-bit mode) TIMING rEQUIREMENTS

      350
    • FIGURE 26-27: ADC Conversion (12-bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000)

      351
    • TABLE 26-42: ADC Conversion (12-bit Mode) TiminG rEQUIREMENTS)

      352
• 27.0 Packaging Information

  353
  • 27.1 Package Marking Information

    353
  • 27.2 Package Details

    354
• Appendix A: Revision History

  359
• The Microchip Web Site

  367
• Customer Change Notification Service

  367
• Customer Support

  367
• Reader Response

  368
• Product Identification System

  369
• Worldwide Sales and Service

  370