Benutzerhandbuch für Philips P89LPC908

Inhaltsverzeichnis

• 1. GENERAL DESCRIPTION

  7
  • PIN CONFIGURATIONS

    7
  • PRODUCT COMPARISON

    8
  • PIN DESCRIPTIONS - P89LPC906

    12
  • PIN DESCRIPTIONS - P89LPC907

    13
  • PIN DESCRIPTIONS - P89LPC908

    14
• 2. CLOCKS

  25
  • ENHANCED CPU

    25
  • CLOCK DEFINITIONS

    25
  • CPU CLOCK (OSCCLK)

    25
  • LOW SPEED OSCILLATOR OPTION - P89LPC906

    25
  • MEDIUM SPEED OSCILLATOR OPTION - P89LPC906

    25
  • HIGH SPEED OSCILLATOR OPTION - P89LPC906

    25
  • OSCILLATOR OPTION SELECTION- P89LPC906

    26
  • CLOCK OUTPUT - P89LPC906

    26
  • ON-CHIP RC OSCILLATOR OPTION

    26
  • WATCHDOG OSCILLATOR OPTION

    26
  • EXTERNAL CLOCK INPUT OPTION - P89LPC906

    27
  • CPU CLOCK (CCLK) WAKEUP DELAY

    27
  • CPU CLOCK (CCLK) MODIFICATION: DIVM REGISTER

    27
  • LOW POWER SELECT (P89LPC906)

    28
• 3. INTERRUPTS

  31
  • INTERRUPT PRIORITY STRUCTURE

    31
  • EXTERNAL INTERRUPT INPUTS

    32
  • EXTERNAL INTERRUPT PIN GLITCH SUPPRESSION

    32
• 4. I/O PORTS

  35
  • PORT CONFIGURATIONS

    35
  • QUASI-BIDIRECTIONAL OUTPUT CONFIGURATION

    35
  • OPEN DRAIN OUTPUT CONFIGURATION

    36
  • INPUT-ONLY CONFIGURATION

    37
  • PUSH-PULL OUTPUT CONFIGURATION

    37
  • PORT 0 ANALOG FUNCTIONS

    37
• 5. TIMERS 0 AND 1

  41
  • MODE 0

    42
  • MODE 2

    42
  • MODE 3

    43
  • MODE 6 - P89LPC907

    43
  • TIMER OVERFLOW TOGGLE OUTPUT - P89LPC907

    45
• 6. REAL-TIME CLOCK/SYSTEM TIMER

  47
  • REAL-TIME CLOCK SOURCE

    47
  • CHANGING RTCS1-0

    50
  • REAL-TIME CLOCK INTERRUPT/WAKE UP

    50
  • RESET SOURCES AFFECTING THE REAL-TIME CLOCK

    50
• 7. POWER MONITORING FUNCTIONS

  53
  • BROWNOUT DETECTION

    53
  • POWER-ON DETECTION

    54
  • POWER REDUCTION MODES

    54
• 8. UART (P89LPC907, P89LPC908)

  59
  • MODE 0

    59
  • MODE 1

    59
  • MODE 2

    59
  • MODE 3

    59
  • BAUD RATE GENERATOR AND SELECTION

    60
  • UPDATING THE BRGR1 AND BRGR0 SFRS

    60
  • FRAMING ERROR

    61
  • BREAK DETECT

    61
  • MORE ABOUT UART MODE 0

    63
  • MORE ABOUT UART MODE 1

    64
  • MORE ABOUT UART MODES 2 AND 3

    65
  • FRAMING ERROR AND RI IN MODES 2 AND 3 WITH SM2 = 1

    65
  • BREAK DETECT

    65
  • DOUBLE BUFFERING

    66
  • DOUBLE BUFFERING IN DIFFERENT MODES

    66
  • TRANSMIT INTERRUPTS WITH DOUBLE BUFFERING ENABLED (MODES 1, 2 AND 3)

    66
  • THE 9TH BIT (BIT 8) IN DOUBLE BUFFERING (MODES 1, 2 AND 3)

    67
  • MULTIPROCESSOR COMMUNICATIONS

    68
  • AUTOMATIC ADDRESS RECOGNITION

    68
• 9. RESET

  71
  • POWER-ON RESET CODE EXECUTION

    71
• 10. ANALOG COMPARATORS

  73
  • COMPARATOR CONFIGURATION

    73
  • INTERNAL REFERENCE VOLTAGE

    74
  • COMPARATOR INTERRUPT

    74
  • COMPARATOR AND POWER REDUCTION MODES

    74
  • COMPARATOR CONFIGURATION EXAMPLE

    75
• 11. KEYPAD INTERRUPT (KBI)

  77
• 12. WATCHDOG TIMER

  79
  • WATCHDOG FUNCTION

    79
  • FEED SEQUENCE

    80
  • WATCHDOG TIMER IN TIMER MODE

    83
  • POWER DOWN OPERATION

    84
  • WATCHDOG CLOCK SOURCE

    84
  • PERIODIC WAKEUP FROM POWER DOWN WITHOUT AN EXTERNAL OSCILLATOR

    85
• 13. ADDITIONAL FEATURES

  87
  • SOFTWARE RESET

    87
  • DUAL DATA POINTERS

    87
• 14. FLASH PROGRAM MEMORY

  89
  • GENERAL DESCRIPTION

    89
  • FEATURES

    89
  • INTRODUCTION TO IAP-LITE

    89
  • USING FLASH AS DATA STORAGE

    89
  • ACCESSING ADDITIONAL FLASH ELEMENTS

    92
  • ERASE-PROGRAMMING ADDITIONAL FLASH ELEMENTS

    93
  • READING ADDITIONAL FLASH ELEMENTS

    93
  • USER CONFIGURATION BYTES

    96
  • USER SECURITY BYTES

    97
• 15. INSTRUCTION SET

  99
• 16. REVISION HISTORY

  103
• 17. INDEX

  105
• Definitions

  110
• Disclaimers

  110