Benutzerhandbuch für Renesas R5S72622

Inhaltsverzeichnis

• Cover

  1
• Notice

  3
• General Precautions on Handling of Product

  4
• Configuration of This Manual

  5
• Preface

  7
• Contents

  11
• Section 1 Overview

  41
  • 1.1 SH7262/7264 Features

    41
  • 1.2 Product Lineup

    52
  • 1.3 Block Diagram

    54
  • 1.4 Pin Assignment

    55
  • 1.5 Pin Functions

    59
  • 1.6 List of Pins

    69
• Section 2 CPU

  89
  • 2.1 Register Configuration

    89
    • 2.1.1 General Registers

      89
    • 2.1.2 Control Registers

      90
    • 2.1.3 System Registers

      92
    • 2.1.4 Register Banks

      93
    • 2.1.5 Initial Values of Registers

      93
  • 2.2 Data Formats

    94
    • 2.2.1 Data Format in Registers

      94
    • 2.2.2 Data Formats in Memory

      94
    • 2.2.3 Immediate Data Format

      95
  • 2.3 Instruction Features

    96
    • 2.3.1 RISC-Type Instruction Set

      96
    • 2.3.2 Addressing Modes

      100
    • 2.3.3 Instruction Format

      105
  • 2.4 Instruction Set

    109
    • 2.4.1 Instruction Set by Classification

      109
    • 2.4.2 Data Transfer Instructions

      115
    • 2.4.3 Arithmetic Operation Instructions

      119
    • 2.4.4 Logic Operation Instructions

      122
    • 2.4.5 Shift Instructions

      123
    • 2.4.6 Branch Instructions

      124
    • 2.4.7 System Control Instructions

      125
    • 2.4.8 Floating-Point Operation Instructions

      127
    • 2.4.9 FPU-Related CPU Instructions

      129
    • 2.4.10 Bit Manipulation Instructions

      130
  • 2.5 Processing States

    132
• Section 3 Floating-Point Unit (FPU)

  135
  • 3.1 Features

    135
  • 3.2 Data Formats

    136
    • 3.2.1 Floating-Point Format

      136
    • 3.2.2 Non-Numbers (NaN)

      139
    • 3.2.3 Denormalized Numbers

      140
  • 3.3 Register Descriptions

    141
    • 3.3.1 Floating-Point Registers

      141
    • 3.3.2 Floating-Point Status/Control Register (FPSCR)

      142
    • 3.3.3 Floating-Point Communication Register (FPUL)

      144
  • 3.4 Rounding

    145
  • 3.5 FPU Exceptions

    146
    • 3.5.1 FPU Exception Sources

      146
    • 3.5.2 FPU Exception Handling

      146
• Section 4 Boot Mode

  149
  • 4.1 Features

    149
  • 4.2 Boot Mode and Pin Function Setting

    149
  • 4.3 Operation

    150
    • 4.3.1 Boot Mode 0

      150
    • 4.3.2 Boot Modes 1 and 3

      150
    • 4.3.3 Boot Mode 2

      151
  • 4.4 Notes

    154
    • 4.4.1 Boot Related Pins

      154
• Section 5 Clock Pulse Generator

  155
  • 5.1 Features

    155
  • 5.2 Input/Output Pins

    158
  • 5.3 Clock Operating Modes

    159
  • 5.4 Register Descriptions

    162
    • 5.4.1 Frequency Control Register (FRQCR)

      162
  • 5.5 Changing the Frequency

    165
    • 5.5.1 Changing the Division Ratio

      165
  • 5.6 Usage of the Clock Pins

    166
    • 5.6.1 In the Case of Inputting an External Clock

      166
    • 5.6.2 In the Case of Using a Crystal Resonator

      167
    • 5.6.3 In the Case of Not Using the Clock Pin

      167
  • 5.7 Oscillation Stabilizing Time

    168
    • 5.7.1 Oscillation Stabilizing Time of the On-chip Crystal Oscillator

      168
    • 5.7.2 Oscillation Stabilizing Time of the PLL circuit

      168
  • 5.8 Notes on Board Design

    169
    • 5.8.1 Note on Using a PLL Oscillation Circuit

      169
• Section 6 Exception Handling

  171
  • 6.1 Overview

    171
    • 6.1.1 Types of Exception Handling and Priority

      171
    • 6.1.2 Exception Handling Operations

      172
    • 6.1.3 Exception Handling Vector Table

      174
  • 6.2 Resets

    177
    • 6.2.1 Input/Output Pins

      177
    • 6.2.2 Types of Reset

      177
    • 6.2.3 Power-On Reset

      179
    • 6.2.4 Manual Reset

      180
  • 6.3 Address Errors

    182
    • 6.3.1 Address Error Sources

      182
    • 6.3.2 Address Error Exception Handling

      183
  • 6.4 Register Bank Errors

    183
    • 6.4.1 Register Bank Error Sources

      183
    • 6.4.2 Register Bank Error Exception Handling

      184
  • 6.5 Interrupts

    184
    • 6.5.1 Interrupt Sources

      184
    • 6.5.2 Interrupt Priority Level

      185
    • 6.5.3 Interrupt Exception Handling

      186
  • 6.6 Exceptions Triggered by Instructions

    187
    • 6.6.1 Types of Exceptions Triggered by Instructions

      187
    • 6.6.2 Trap Instructions

      188
    • 6.6.3 Slot Illegal Instructions

      188
    • 6.6.4 General Illegal Instructions

      189
    • 6.6.5 Integer Division Exceptions

      189
    • 6.6.6 FPU Exceptions

      190
  • 6.7 When Exception Sources Are Not Accepted

    191
  • 6.8 Stack Status after Exception Handling Ends

    191
  • 6.9 Usage Notes

    193
    • 6.9.1 Value of Stack Pointer (SP)

      193
    • 6.9.2 Value of Vector Base Register (VBR)

      193
    • 6.9.3 Address Errors Caused by Stacking of Address Error Exception Handling

      193
    • 6.9.4 Interrupt Control via Modification of Interrupt Mask Bits

      193
    • 6.9.5 Note before Exception Handling Begins Running

      194
• Section 7 Interrupt Controller

  197
  • 7.1 Features

    197
  • 7.2 Input/Output Pins

    199
  • 7.3 Register Descriptions

    200
    • 7.3.1 Interrupt Priority Registers 01, 02, 05 to 22 (IPR01, IPR02, IPR05 to IPR22)

      202
    • 7.3.2 Interrupt Control Register 0 (ICR0)

      204
    • 7.3.3 Interrupt Control Register 1 (ICR1)

      206
    • 7.3.4 Interrupt Control Register 2 (ICR2)

      207
    • 7.3.5 IRQ Interrupt Request Register (IRQRR)

      208
    • 7.3.6 PINT Interrupt Enable Register (PINTER)

      209
    • 7.3.7 PINT Interrupt Request Register (PIRR)

      210
    • 7.3.8 Bank Control Register (IBCR)

      211
    • 7.3.9 Bank Number Register (IBNR)

      212
  • 7.4 Interrupt Sources

    213
    • 7.4.1 NMI Interrupt

      213
    • 7.4.2 User Debugging Interface Interrupt

      214
    • 7.4.3 IRQ Interrupts

      214
    • 7.4.4 PINT Interrupts

      215
    • 7.4.5 On-Chip Peripheral Module Interrupts

      216
  • 7.5 Interrupt Exception Handling Vector Table and Priority

    217
  • 7.6 Operation

    231
    • 7.6.1 Interrupt Operation Sequence

      231
    • 7.6.2 Stack after Interrupt Exception Handling

      234
  • 7.7 Interrupt Response Time

    235
  • 7.8 Register Banks

    241
    • 7.8.1 Banked Register and Input/Output of Banks

      242
    • 7.8.2 Bank Save and Restore Operations

      242
    • 7.8.3 Save and Restore Operations after Saving to All Banks

      244
    • 7.8.4 Register Bank Exception

      245
    • 7.8.5 Register Bank Error Exception Handling

      245
  • 7.9 Data Transfer with Interrupt Request Signals

    246
    • 7.9.1 Handling Interrupt Request Signals as Sources for CPU Interrupt but Not Direct Memory Access Controller Activating

      247
    • 7.9.2 Handling Interrupt Request Signals as Sources for Activating Direct Memory Access Controller but Not CPU Interrupt

      247
  • 7.10 Usage Note

    248
    • 7.10.1 Timing to Clear an Interrupt Source

      248
• Section 8 Cache

  249
  • 8.1 Features

    249
    • 8.1.1 Cache Structure

      249
  • 8.2 Register Descriptions

    252
    • 8.2.1 Cache Control Register 1 (CCR1)

      252
    • 8.2.2 Cache Control Register 2 (CCR2)

      254
  • 8.3 Operation

    258
    • 8.3.1 Searching Cache

      258
    • 8.3.2 Read Access

      260
    • 8.3.3 Prefetch Operation (Only for Operand Cache)

      260
    • 8.3.4 Write Operation (Only for Operand Cache)

      261
    • 8.3.5 Write-Back Buffer (Only for Operand Cache)

      261
    • 8.3.6 Coherency of Cache and External Memory or Large-Capacity On-Chip RAM

      263
  • 8.4 Memory-Mapped Cache

    264
    • 8.4.1 Address Array

      264
    • 8.4.2 Data Array

      265
    • 8.4.3 Usage Examples

      267
    • 8.4.4 Usage Notes

      268
• Section 9 Bus State Controller

  269
  • 9.1 Features

    269
  • 9.2 Input/Output Pins

    272
  • 9.3 Area Overview

    274
    • 9.3.1 Address Map

      274
    • 9.3.2 Data Bus Width and Endian Specification of Each Area and Related Pin Settings Depending on Boot Mode

      275
  • 9.4 Register Descriptions

    277
    • 9.4.1 Common Control Register (CMNCR)

      279
    • 9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 6)

      282
    • 9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 6)

      287
    • 9.4.4 SDRAM Control Register (SDCR)

      320
    • 9.4.5 Refresh Timer Control/Status Register (RTCSR)

      324
    • 9.4.6 Refresh Timer Counter (RTCNT)

      326
    • 9.4.7 Refresh Time Constant Register (RTCOR)

      327
    • 9.4.8 AC Characteristics Switching Register (ACSWR)

      328
    • 9.4.9 AC Characteristics Switching Key Register (ACKEYR)

      329
    • 9.4.10 Sequence to Write to ACSWR

      330
  • 9.5 Operation

    331
    • 9.5.1 Endian/Access Size and Data Alignment

      331
    • 9.5.2 Normal Space Interface

      334
    • 9.5.3 Access Wait Control

      338
    • 9.5.4 CSn Assert Period Expansion

      340
    • 9.5.5 MPX-I/O Interface

      341
    • 9.5.6 SDRAM Interface

      346
    • 9.5.7 Burst ROM (Clocked Asynchronous) Interface

      382
    • 9.5.8 SRAM Interface with Byte Selection

      384
    • 9.5.9 PCMCIA Interface

      388
    • 9.5.10 Burst ROM (Clocked Synchronous) Interface

      395
    • 9.5.11 Wait between Access Cycles

      396
    • 9.5.12 Bus Arbitration

      404
    • 9.5.13 Others

      406
• Section 10 Direct Memory Access Controller

  411
  • 10.1 Features

    411
  • 10.2 Input/Output Pins

    414
  • 10.3 Register Descriptions

    415
    • 10.3.1 DMA Source Address Registers (SAR)

      424
    • 10.3.2 DMA Destination Address Registers (DAR)

      424
    • 10.3.3 DMA Transfer Count Registers (DMATCR)

      425
    • 10.3.4 DMA Channel Control Registers (CHCR)

      425
    • 10.3.5 DMA Reload Source Address Registers (RSAR)

      436
    • 10.3.6 DMA Reload Destination Address Registers (RDAR)

      436
    • 10.3.7 DMA Reload Transfer Count Registers (RDMATCR)

      437
    • 10.3.8 DMA Operation Register (DMAOR)

      438
    • 10.3.9 DMA Extension Resource Selectors 0 to 7 (DMARS0 to DMARS7)

      442
  • 10.4 Operation

    448
    • 10.4.1 Transfer Flow

      448
    • 10.4.2 DMA Transfer Requests

      450
    • 10.4.3 Channel Priority

      457
    • 10.4.4 DMA Transfer Types

      457
    • 10.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing

      466
  • 10.5 Usage Notes

    470
    • 10.5.1 Timing of DACK and TEND Outputs

      470
    • 10.5.2 Notes on Using Flag Bits

      470
• Section 11 Multi-Function Timer Pulse Unit 2

  471
  • 11.1 Features

    471
  • 11.2 Input/Output Pins

    476
  • 11.3 Register Descriptions

    477
    • 11.3.1 Timer Control Register (TCR)

      481
    • 11.3.2 Timer Mode Register (TMDR)

      485
    • 11.3.3 Timer I/O Control Register (TIOR)

      488
    • 11.3.4 Timer Interrupt Enable Register (TIER)

      506
    • 11.3.5 Timer Status Register (TSR)

      509
    • 11.3.6 Timer Buffer Operation Transfer Mode Register (TBTM)

      514
    • 11.3.7 Timer Input Capture Control Register (TICCR)

      515
    • 11.3.8 Timer A/D Converter Start Request Control Register (TADCR)

      517
    • 11.3.9 Timer A/D Converter Start Request Cycle Set Registers (TADCORA_4 and TADCORB_4)

      520
    • 11.3.10 Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA_4 and TADCOBRB_4)

      520
    • 11.3.11 Timer Counter (TCNT)

      521
    • 11.3.12 Timer General Register (TGR)

      521
    • 11.3.13 Timer Start Register (TSTR)

      522
    • 11.3.14 Timer Synchronous Register (TSYR)

      523
    • 11.3.15 Timer Read/Write Enable Register (TRWER)

      525
    • 11.3.16 Timer Output Master Enable Register (TOER)

      526
    • 11.3.17 Timer Output Control Register 1 (TOCR1)

      528
    • 11.3.18 Timer Output Control Register 2 (TOCR2)

      531
    • 11.3.19 Timer Output Level Buffer Register (TOLBR)

      534
    • 11.3.20 Timer Gate Control Register (TGCR)

      535
    • 11.3.21 Timer Subcounter (TCNTS)

      537
    • 11.3.22 Timer Dead Time Data Register (TDDR)

      538
    • 11.3.23 Timer Cycle Data Register (TCDR)

      538
    • 11.3.24 Timer Cycle Buffer Register (TCBR)

      539
    • 11.3.25 Timer Interrupt Skipping Set Register (TITCR)

      539
    • 11.3.26 Timer Interrupt Skipping Counter (TITCNT)

      541
    • 11.3.27 Timer Buffer Transfer Set Register (TBTER)

      542
    • 11.3.28 Timer Dead Time Enable Register (TDER)

      544
    • 11.3.29 Timer Waveform Control Register (TWCR)

      545
    • 11.3.30 Bus Master Interface

      546
  • 11.4 Operation

    547
    • 11.4.1 Basic Functions

      547
    • 11.4.2 Synchronous Operation

      553
    • 11.4.3 Buffer Operation

      555
    • 11.4.4 Cascaded Operation

      559
    • 11.4.5 PWM Modes

      564
    • 11.4.6 Phase Counting Mode

      569
    • 11.4.7 Reset-Synchronized PWM Mode

      576
    • 11.4.8 Complementary PWM Mode

      579
    • 11.4.9 A/D Converter Start Request Delaying Function

      618
    • 11.4.10 TCNT Capture at Crest and/or Trough in Complementary PWM Operation

      622
  • 11.5 Interrupt Sources

    623
    • 11.5.1 Interrupt Sources and Priorities

      623
    • 11.5.2 Activation of Direct Memory Access Controller

      625
    • 11.5.3 A/D Converter Activation

      625
  • 11.6 Operation Timing

    627
    • 11.6.1 Input/Output Timing

      627
    • 11.6.2 Interrupt Signal Timing

      634
  • 11.7 Usage Notes

    638
    • 11.7.1 Module Standby Mode Setting

      638
    • 11.7.2 Input Clock Restrictions

      638
    • 11.7.3 Caution on Period Setting

      639
    • 11.7.4 Contention between TCNT Write and Clear Operations

      639
    • 11.7.5 Contention between TCNT Write and Increment Operations

      640
    • 11.7.6 Contention between TGR Write and Compare Match

      641
    • 11.7.7 Contention between Buffer Register Write and Compare Match

      642
    • 11.7.8 Contention between Buffer Register Write and TCNT Clear

      643
    • 11.7.9 Contention between TGR Read and Input Capture

      644
    • 11.7.10 Contention between TGR Write and Input Capture

      645
    • 11.7.11 Contention between Buffer Register Write and Input Capture

      646
    • 11.7.12 TCNT2 Write and Overflow/Underflow Contention in Cascade Connection

      646
    • 11.7.13 Counter Value during Complementary PWM Mode Stop

      648
    • 11.7.14 Buffer Operation Setting in Complementary PWM Mode

      648
    • 11.7.15 Reset Sync PWM Mode Buffer Operation and Compare Match Flag

      649
    • 11.7.16 Overflow Flags in Reset Synchronous PWM Mode

      650
    • 11.7.17 Contention between Overflow/Underflow and Counter Clearing

      651
    • 11.7.18 Contention between TCNT Write and Overflow/Underflow

      652
    • 11.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to Reset-Synchronized PWM Mode

      652
    • 11.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode

      653
    • 11.7.21 Interrupts in Module Standby Mode

      653
    • 11.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection

      653
    • 11.7.23 Notes on Output Waveform Control During Synchronous Counter Clearing in Complementary PWM Mode

      654
  • 11.8 Output Pin Initialization for Multi-Function Timer Pulse Unit 2

    656
    • 11.8.1 Operating Modes

      656
    • 11.8.2 Reset Start Operation

      656
    • 11.8.3 Operation in Case of Re-Setting Due to Error during Operation, etc.

      657
    • 11.8.4 Overview of Initialization Procedures and Mode Transitions in Case of Error during Operation, etc.

      658
• Section 12 Compare Match Timer

  689
  • 12.1 Features

    689
  • 12.2 Register Descriptions

    690
    • 12.2.1 Compare Match Timer Start Register (CMSTR)

      691
    • 12.2.2 Compare Match Timer Control/Status Register (CMCSR)

      692
    • 12.2.3 Compare Match Counter (CMCNT)

      694
    • 12.2.4 Compare Match Constant Register (CMCOR)

      694
  • 12.3 Operation

    695
    • 12.3.1 Interval Count Operation

      695
    • 12.3.2 CMCNT Count Timing

      695
  • 12.4 Interrupts

    696
    • 12.4.1 Interrupt Sources and DMA Transfer Requests

      696
    • 12.4.2 Timing of Compare Match Flag Setting

      696
    • 12.4.3 Timing of Compare Match Flag Clearing

      697
  • 12.5 Usage Notes

    698
    • 12.5.1 Conflict between Write and Compare-Match Processes of CMCNT

      698
    • 12.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT

      699
    • 12.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT

      700
    • 12.5.4 Compare Match between CMCNT and CMCOR

      700
• Section 13 Watchdog Timer

  701
  • 13.1 Features

    701
  • 13.2 Input/Output Pin

    702
  • 13.3 Register Descriptions

    703
    • 13.3.1 Watchdog Timer Counter (WTCNT)

      703
    • 13.3.2 Watchdog Timer Control/Status Register (WTCSR)

      704
    • 13.3.3 Watchdog Reset Control/Status Register (WRCSR)

      707
    • 13.3.4 Notes on Register Access

      708
  • 13.4 Usage

    710
    • 13.4.1 Canceling Software Standby Mode

      710
    • 13.4.2 Using Watchdog Timer Mode

      710
    • 13.4.3 Using Interval Timer Mode

      712
  • 13.5 Usage Notes

    713
    • 13.5.1 Timer Variation

      713
    • 13.5.2 Prohibition against Setting H'FF to WTCNT

      713
    • 13.5.3 Interval Timer Overflow Flag

      713
    • 13.5.4 System Reset by WDTOVF Signal

      714
    • 13.5.5 Manual Reset in Watchdog Timer Mode

      714
    • 13.5.6 Internal Reset in Watchdog Timer Mode

      714
• Section 14 Realtime Clock

  715
  • 14.1 Features

    715
  • 14.2 Input/Output Pin

    717
  • 14.3 Register Descriptions

    717
    • 14.3.1 64-Hz Counter (R64CNT)

      718
    • 14.3.2 Second Counter (RSECCNT)

      719
    • 14.3.3 Minute Counter (RMINCNT)

      720
    • 14.3.4 Hour Counter (RHRCNT)

      721
    • 14.3.5 Day of Week Counter (RWKCNT)

      722
    • 14.3.6 Date Counter (RDAYCNT)

      723
    • 14.3.7 Month Counter (RMONCNT)

      724
    • 14.3.8 Year Counter (RYRCNT)

      725
    • 14.3.9 Second Alarm Register (RSECAR)

      726
    • 14.3.10 Minute Alarm Register (RMINAR)

      727
    • 14.3.11 Hour Alarm Register (RHRAR)

      728
    • 14.3.12 Day of Week Alarm Register (RWKAR)

      729
    • 14.3.13 Date Alarm Register (RDAYAR)

      730
    • 14.3.14 Month Alarm Register (RMONAR)

      731
    • 14.3.15 Year Alarm Register (RYRAR)

      732
    • 14.3.16 Control Register 1 (RCR1)

      733
    • 14.3.17 Control Register 2 (RCR2)

      735
    • 14.3.18 Control Register 3 (RCR3)

      737
    • 14.3.19 Control Register 5 (RCR5)

      738
    • 14.3.20 Frequency Register H/L (RFRH/L)

      739
  • 14.4 Operation

    741
    • 14.4.1 Initial Settings of Registers after Power-On

      741
    • 14.4.2 Setting Time

      741
    • 14.4.3 Reading Time

      742
    • 14.4.4 Alarm Function

      743
  • 14.5 Usage Notes

    744
    • 14.5.1 Register Writing during Count

      744
    • 14.5.2 Use of Realtime Clock Periodic Interrupts

      744
    • 14.5.3 Transition to Standby Mode after Setting Register

      744
    • 14.5.4 Usage Notes when Writing to and Reading the Register

      745
• Section 15 Serial Communication Interface with FIFO

  747
  • 15.1 Features

    747
  • 15.2 Input/Output Pins

    750
  • 15.3 Register Descriptions

    751
    • 15.3.1 Receive Shift Register (SCRSR)

      755
    • 15.3.2 Receive FIFO Data Register (SCFRDR)

      755
    • 15.3.3 Transmit Shift Register (SCTSR)

      756
    • 15.3.4 Transmit FIFO Data Register (SCFTDR)

      756
    • 15.3.5 Serial Mode Register (SCSMR)

      757
    • 15.3.6 Serial Control Register (SCSCR)

      760
    • 15.3.7 Serial Status Register (SCFSR)

      764
    • 15.3.8 Bit Rate Register (SCBRR)

      772
    • 15.3.9 FIFO Control Register (SCFCR)

      778
    • 15.3.10 FIFO Data Count Set Register (SCFDR)

      781
    • 15.3.11 Serial Port Register (SCSPTR)

      782
    • 15.3.12 Line Status Register (SCLSR)

      785
    • 15.3.13 Serial Extension Mode Register (SCEMR)

      786
  • 15.4 Operation

    787
    • 15.4.1 Overview

      787
    • 15.4.2 Operation in Asynchronous Mode

      790
    • 15.4.3 Operation in Clock Synchronous Mode

      801
  • 15.5 Interrupts

    810
  • 15.6 Usage Notes

    811
    • 15.6.1 SCFTDR Writing and TDFE Flag

      811
    • 15.6.2 SCFRDR Reading and RDF Flag

      811
    • 15.6.3 Restriction on Direct Memory Controller Usage

      812
    • 15.6.4 Break Detection and Processing

      812
    • 15.6.5 Sending a Break Signal

      812
    • 15.6.6 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode)

      812
    • 15.6.7 Selection of Base Clock in Asynchronous Mode

      814
• Section 16 Renesas Serial Peripheral Interface

  815
  • 16.1 Features

    815
  • 16.2 Input/Output Pins

    818
  • 16.3 Register Descriptions

    819
    • 16.3.1 Control Register (SPCR)

      821
    • 16.3.2 Slave Select Polarity Register (SSLP)

      823
    • 16.3.3 Pin Control Register (SPPCR)

      824
    • 16.3.4 Status Register (SPSR)

      826
    • 16.3.5 Data Register (SPDR)

      829
    • 16.3.6 Sequence Control Register (SPSCR)

      830
    • 16.3.7 Sequence Status Register (SPSSR)

      832
    • 16.3.8 Bit Rate Register (SPBR)

      833
    • 16.3.9 Data Control Register (SPDCR)

      835
    • 16.3.10 Clock Delay Register (SPCKD)

      837
    • 16.3.11 Slave Select Negation Delay Register (SSLND)

      838
    • 16.3.12 Next-Access Delay Register (SPND)

      839
    • 16.3.13 Command Register (SPCMD)

      840
    • 16.3.14 Buffer Control Register (SPBFCR)

      845
    • 16.3.15 Buffer Data Count Setting Register (SPBFDR)

      847
  • 16.4 Operation

    848
    • 16.4.1 Overview of Operations

      848
    • 16.4.2 Pin Control

      849
    • 16.4.3 System Configuration Example

      850
    • 16.4.4 Transfer Format

      853
    • 16.4.5 Data Format

      855
    • 16.4.6 Error Detection

      867
    • 16.4.7 Initialization

      872
    • 16.4.8 SPI Operation

      873
    • 16.4.9 Error Handling

      886
    • 16.4.10 Loopback Mode

      887
    • 16.4.11 Interrupt Sources

      888
• Section 17 I2C Bus Interface 3

  889
  • 17.1 Features

    889
  • 17.2 Input/Output Pins

    891
  • 17.3 Register Descriptions

    892
    • 17.3.1 I2C Bus Control Register 1 (ICCR1)

      893
    • 17.3.2 I2C Bus Control Register 2 (ICCR2)

      896
    • 17.3.3 I2C Bus Mode Register (ICMR)

      898
    • 17.3.4 I2C Bus Interrupt Enable Register (ICIER)

      900
    • 17.3.5 I2C Bus Status Register (ICSR)

      902
    • 17.3.6 Slave Address Register (SAR)

      905
    • 17.3.7 I2C Bus Transmit Data Register (ICDRT)

      905
    • 17.3.8 I2C Bus Receive Data Register (ICDRR)

      906
    • 17.3.9 I2C Bus Shift Register (ICDRS)

      906
    • 17.3.10 NF2CYC Register (NF2CYC)

      907
  • 17.4 Operation

    908
    • 17.4.1 I2C Bus Format

      908
    • 17.4.2 Master Transmit Operation

      909
    • 17.4.3 Master Receive Operation

      911
    • 17.4.4 Slave Transmit Operation

      913
    • 17.4.5 Slave Receive Operation

      916
    • 17.4.6 Clocked Synchronous Serial Format

      917
    • 17.4.7 Noise Filter

      921
    • 17.4.8 Example of Use

      922
  • 17.5 Interrupt Requests

    926
  • 17.6 Bit Synchronous Circuit

    927
  • 17.7 Usage Notes

    930
    • 17.7.1 Note on Setting for Multi-Master Operation

      930
    • 17.7.2 Note on Master Receive Mode

      930
    • 17.7.3 Note on Setting ACKBT in Master Receive Mode

      930
    • 17.7.4 Note on the States of Bits MST and TRN when Arbitration is Lost

      931
    • 17.7.5 Note on I2C-bus Interface Master Receive Mode

      931
    • 17.7.6 Note on IICRST and BBSY bits

      931
    • 17.7.7 Note on Issuance of Stop Conditions in Master Transmit Mode while ACKE = 1

      931
• Section 18 Serial Sound Interface

  933
  • 18.1 Features

    933
  • 18.2 Input/Output Pins

    936
  • 18.3 Register Description

    937
    • 18.3.1 Control Register (SSICR)

      939
    • 18.3.2 Status Register (SSISR)

      946
    • 18.3.3 Transmit Data Register (SSITDR)

      950
    • 18.3.4 Receive Data Register (SSIRDR)

      950
    • 18.3.5 FIFO Control Register (SSIFCR)

      951
    • 18.3.6 FIFO Status Register (SSIFSR)

      954
    • 18.3.7 Transmit FIFO Data Register (SSIFTDR)

      957
    • 18.3.8 Receive FIFO Data Register (SSIFRDR)

      957
  • 18.4 Operation Description

    958
    • 18.4.1 Bus Format

      958
    • 18.4.2 Non-Compressed Modes

      959
    • 18.4.3 Operation Modes

      969
    • 18.4.4 Transmit Operation

      970
    • 18.4.5 Receive Operation

      973
    • 18.4.6 Serial Bit Clock Control

      976
  • 18.5 Usage Notes

    977
    • 18.5.1 Limitations from Underflow or Overflow during DMA Operation

      977
    • 18.5.2 Note on Changing Mode from Master Transceiver to Master Receiver

      977
• Section 19 Serial I/O with FIFO

  979
  • 19.1 Features

    979
  • 19.2 Input/Output Pins

    981
  • 19.3 Register Descriptions

    982
    • 19.3.1 Mode Register (SIMDR)

      983
    • 19.3.2 Control Register (SICTR)

      985
    • 19.3.3 Transmit Data Register (SITDR)

      988
    • 19.3.4 Receive Data Register (SIRDR)

      989
    • 19.3.5 Status Register (SISTR)

      990
    • 19.3.6 Interrupt Enable Register (SIIER)

      995
    • 19.3.7 FIFO Control Register (SIFCTR)

      997
    • 19.3.8 Clock Select Register (SISCR)

      999
    • 19.3.9 Transmit Data Assign Register (SITDAR)

      1000
    • 19.3.10 Receive Data Assign Register (SIRDAR)

      1002
  • 19.4 Operation

    1003
    • 19.4.1 Serial Clocks

      1003
    • 19.4.2 Serial Timing

      1004
    • 19.4.3 Transfer Data Format

      1005
    • 19.4.4 Register Allocation of Transfer Data

      1006
    • 19.4.5 FIFO

      1008
    • 19.4.6 Transmit and Receive Procedures

      1010
    • 19.4.7 Interrupts

      1015
    • 19.4.8 Transmit and Receive Timing

      1017
• Section 20 Controller Area Network

  1021
  • 20.1 Summary

    1021
    • 20.1.1 Overview

      1021
    • 20.1.2 Scope

      1021
    • 20.1.3 Audience

      1021
    • 20.1.4 References

      1021
    • 20.1.5 Features

      1022
  • 20.2 Architecture

    1023
  • 20.3 Programming Model - Overview

    1026
    • 20.3.1 Memory Map

      1026
    • 20.3.2 Mailbox Structure

      1028
    • 20.3.3 Control Registers

      1044
    • 20.3.4 Mailbox Registers

      1065
    • 20.3.5 Timer Registers

      1079
  • 20.4 Application Note

    1092
    • 20.4.1 Test Mode Settings

      1092
    • 20.4.2 Configuration of This Module

      1094
    • 20.4.3 Message Transmission Sequence

      1098
    • 20.4.4 Message Receive Sequence

      1113
    • 20.4.5 Reconfiguration of Mailbox

      1115
  • 20.5 Interrupt Sources

    1117
  • 20.6 DMAC Interface

    1118
  • 20.7 CAN Bus Interface

    1119
  • 20.8 Setting I/O Ports

    1120
  • 20.9 Usage Notes

    1122
    • 20.9.1 Notes on Port Setting for Multiple Channels Used as Single Channel

      1122
• Section 21 IEBusTM Controller

  1123
  • 21.1 Features

    1123
    • 21.1.1 IEBus Communications Protocol

      1124
    • 21.1.2 Communications Protocol

      1128
    • 21.1.3 Transfer Data (Data Field Contents)

      1136
    • 21.1.4 Bit Format

      1139
    • 21.1.5 Configuration

      1140
  • 21.2 Input/Output Pins

    1141
  • 21.3 Register Descriptions

    1142
    • 21.3.1 IEBus Control Register (IECTR)

      1144
    • 21.3.2 IEBus Command Register (IECMR)

      1145
    • 21.3.3 IEBus Master Control Register (IEMCR)

      1147
    • 21.3.4 IEBus Master Unit Address Register 1 (IEAR1)

      1149
    • 21.3.5 IEBus Master Unit Address Register 2 (IEAR2)

      1150
    • 21.3.6 IEBus Slave Address Setting Register 1 (IESA1)

      1150
    • 21.3.7 IEBus Slave Address Setting Register 2 (IESA2)

      1151
    • 21.3.8 IEBus Transmit Message Length Register (IETBFL)

      1152
    • 21.3.9 IEBus Reception Master Address Register 1 (IEMA1)

      1153
    • 21.3.10 IEBus Reception Master Address Register 2 (IEMA2)

      1154
    • 21.3.11 IEBus Receive Control Field Register (IERCTL)

      1155
    • 21.3.12 IEBus Receive Message Length Register (IERBFL)

      1156
    • 21.3.13 IEBus Lock Address Register 1 (IELA1)

      1156
    • 21.3.14 IEBus Lock Address Register 2 (IELA2)

      1157
    • 21.3.15 IEBus General Flag Register (IEFLG)

      1158
    • 21.3.16 IEBus Transmit Status Register (IETSR)

      1161
    • 21.3.17 IEBus Transmit Interrupt Enable Register (IEIET)

      1165
    • 21.3.18 IEBus Receive Status Register (IERSR)

      1167
    • 21.3.19 IEBus Receive Interrupt Enable Register (IEIER)

      1171
    • 21.3.20 IEBus Clock Selection Register (IECKSR)

      1173
    • 21.3.21 IEBus Transmit Data Buffer 001 to 128 (IETB001 to IETB128)

      1174
    • 21.3.22 IEBus Receive Data Buffer 001 to 128 (IERB001 to IERB128)

      1175
  • 21.4 Data Format

    1176
    • 21.4.1 Transmission Format

      1176
    • 21.4.2 Reception Format

      1177
  • 21.5 Software Control Flows

    1178
    • 21.5.1 Initial Setting

      1178
    • 21.5.2 Master Transmission

      1179
    • 21.5.3 Slave Reception

      1180
    • 21.5.4 Master Reception

      1181
    • 21.5.5 Slave Transmission

      1182
  • 21.6 Operation Timing

    1183
    • 21.6.1 Master Transmit Operation

      1183
    • 21.6.2 Slave Receive Operation

      1184
    • 21.6.3 Master Receive Operation

      1185
    • 21.6.4 Slave Transmit Operation

      1186
  • 21.7 Interrupt Sources

    1187
  • 21.8 Usage Notes

    1189
    • 21.8.1 Note on Operation when Transfer is Incomplete after Transfer of the Maximum Number of Bytes

      1189
• Section 22 Renesas SPDIF Interface

  1191
  • 22.1 Overview

    1191
  • 22.2 Features

    1191
  • 22.3 Functional Block Diagram

    1192
  • 22.4 Input/Output Pins

    1193
  • 22.5 Renesas SPDIF (IEC60958) Frame Format

    1193
  • 22.6 Register

    1195
  • 22.7 Register Descriptions

    1196
    • 22.7.1 Control Register (CTRL)

      1196
    • 22.7.2 Status Register (STAT)

      1201
    • 22.7.3 Transmitter Channel 1 Audio Register (TLCA)

      1205
    • 22.7.4 Transmitter Channel 2 Audio Register (TRCA)

      1206
    • 22.7.5 Transmitter DMA Audio Data Register (TDAD)

      1207
    • 22.7.6 Transmitter User Data Register (TUI)

      1208
    • 22.7.7 Transmitter Channel 1 Status Register (TLCS)

      1209
    • 22.7.8 Transmitter Channel 2 Status Register (TRCS)

      1211
    • 22.7.9 Receiver Channel 1 Audio Register (RLCA)

      1213
    • 22.7.10 Receiver Channel 2 Audio Register (RRCA)

      1214
    • 22.7.11 Receiver DMA Audio Data (RDAD)

      1215
    • 22.7.12 Receiver User Data Register (RUI)

      1216
    • 22.7.13 Receiver Channel 1 Status Register (RLCS)

      1217
    • 22.7.14 Receiver Channel 2 Status Register (RRCS)

      1219
  • 22.8 Functional Description.Transmitter

    1221
    • 22.8.1 Transmitter Module

      1221
    • 22.8.2 Transmitter Module Initialization

      1222
    • 22.8.3 Initial Settings for Transmitter Module

      1222
    • 22.8.4 Transmitter Module Data Transfer

      1223
  • 22.9 Functional Description.Receiver

    1225
    • 22.9.1 Receiver Module

      1225
    • 22.9.2 Receiver Module Initialization

      1226
    • 22.9.3 Receiver Module Data Transfer

      1226
  • 22.10 Disabling the Module

    1229
    • 22.10.1 Transmitter and Receiver Idle

      1229
  • 22.11 Compressed Mode Data

    1229
  • 22.12 References

    1229
  • 22.13 Usage Notes

    1230
    • 22.13.1 Clearing TUIR

      1230
    • 22.13.2 Frequency of Clock Input for Audio

      1230
• Section 23 CD-ROM Decoder

  1231
  • 23.1 Features

    1231
    • 23.1.1 Formats Supported by CD-ROM Decoder

      1232
  • 23.2 Block Diagrams

    1233
  • 23.3 Register Descriptions

    1237
    • 23.3.1 Enable Control Register (CROMEN)

      1240
    • 23.3.2 Sync Code-Based Synchronization Control Register (CROMSY0)

      1241
    • 23.3.3 Decoding Mode Control Register (CROMCTL0)

      1242
    • 23.3.4 EDC/ECC Check Control Register (CROMCTL1)

      1244
    • 23.3.5 Automatic Decoding Stop Control Register (CROMCTL3)

      1245
    • 23.3.6 Decoding Option Setting Control Register (CROMCTL4)

      1246
    • 23.3.7 HEAD20 to HEAD22 Representation Control Register (CROMCTL5)

      1248
    • 23.3.8 Sync Code Status Register (CROMST0)

      1249
    • 23.3.9 Post-ECC Header Error Status Register (CROMST1)

      1250
    • 23.3.10 Post-ECC Subheader Error Status Register (CROMST3)

      1251
    • 23.3.11 Header/Subheader Validity Check Status Register (CROMST4)

      1252
    • 23.3.12 Mode Determination and Link Sector Detection Status Register (CROMST5)

      1253
    • 23.3.13 ECC/EDC Error Status Register (CROMST6)

      1254
    • 23.3.14 Buffer Status Register (CBUFST0)

      1256
    • 23.3.15 Decoding Stoppage Source Status Register (CBUFST1)

      1257
    • 23.3.16 Buffer Overflow Status Register (CBUFST2)

      1258
    • 23.3.17 Pre-ECC Correction Header: Minutes Data Register (HEAD00)

      1258
    • 23.3.18 Pre-ECC Correction Header: Seconds Data Register (HEAD01)

      1259
    • 23.3.19 Pre-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD02)

      1259
    • 23.3.20 Pre-ECC Correction Header: Mode Data Register (HEAD03)

      1260
    • 23.3.21 Pre-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD00)

      1260
    • 23.3.22 Pre-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD01)

      1261
    • 23.3.23 Pre-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD02)

      1261
    • 23.3.24 Pre-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD03)

      1262
    • 23.3.25 Pre-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD04)

      1262
    • 23.3.26 Pre-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD05)

      1263
    • 23.3.27 Pre-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD06)

      1263
    • 23.3.28 Pre-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD07)

      1264
    • 23.3.29 Post-ECC Correction Header: Minutes Data Register (HEAD20)

      1264
    • 23.3.30 Post-ECC Correction Header: Seconds Data Register (HEAD21)

      1265
    • 23.3.31 Post-ECC Correction Header: Frames (1/75 Second) Data Register (HEAD22)

      1265
    • 23.3.32 Post-ECC Correction Header: Mode Data Register (HEAD23)

      1266
    • 23.3.33 Post-ECC Correction Subheader: File Number (Byte 16) Data Register (SHEAD20)

      1266
    • 23.3.34 Post-ECC Correction Subheader: Channel Number (Byte 17) Data Register (SHEAD21)

      1267
    • 23.3.35 Post-ECC Correction Subheader: Sub-Mode (Byte 18) Data Register (SHEAD22)

      1267
    • 23.3.36 Post-ECC Correction Subheader: Data Type (Byte 19) Data Register (SHEAD23)

      1268
    • 23.3.37 Post-ECC Correction Subheader: File Number (Byte 20) Data Register (SHEAD24)

      1268
    • 23.3.38 Post-ECC Correction Subheader: Channel Number (Byte 21) Data Register (SHEAD25)

      1269
    • 23.3.39 Post-ECC Correction Subheader: Sub-Mode (Byte 22) Data Register (SHEAD26)

      1269
    • 23.3.40 Post-ECC Correction Subheader: Data Type (Byte 23) Data Register (SHEAD27)

      1270
    • 23.3.41 Automatic Buffering Setting Control Register 0 (CBUFCTL0)

      1270
    • 23.3.42 Automatic Buffering Start Sector Setting: Minutes Control Register (CBUFCTL1)

      1272
    • 23.3.43 Automatic Buffering Start Sector Setting: Seconds Control Register (CBUFCTL2)

      1272
    • 23.3.44 Automatic Buffering Start Sector Setting: Frames Control Register (CBUFCTL3)

      1273
    • 23.3.45 ISY Interrupt Source Mask Control Register (CROMST0M)

      1273
    • 23.3.46 CD-ROM Decoder Reset Control Register (ROMDECRST)

      1274
    • 23.3.47 CD-ROM Decoder Reset Status Register (RSTSTAT)

      1275
    • 23.3.48 Serial Sound Interface Data Control Register (SSI)

      1275
    • 23.3.49 Interrupt Flag Register (INTHOLD)

      1278
    • 23.3.50 Interrupt Source Mask Control Register (INHINT)

      1279
    • 23.3.51 CD-ROM Decoder Stream Data Input Register (STRMDIN0)

      1280
    • 23.3.52 CD-ROM Decoder Stream Data Input Register (STRMDIN2)

      1280
    • 23.3.53 CD-ROM Decoder Stream Data Output Register (STRMDOUT0)

      1281
  • 23.4 Operation

    1282
    • 23.4.1 Endian Conversion for Data in the Input Stream

      1282
    • 23.4.2 Sync Code Maintenance Function

      1283
    • 23.4.3 Error Correction

      1288
    • 23.4.4 Automatic Decoding Stop Function

      1289
    • 23.4.5 Buffering Format

      1290
    • 23.4.6 Target-Sector Buffering Function

      1292
  • 23.5 Interrupt Sources

    1294
    • 23.5.1 Interrupt and DMA Transfer Request Signals

      1294
    • 23.5.2 Timing of Status Registers Updates

      1296
  • 23.6 Usage Notes

    1296
    • 23.6.1 Stopping and Resuming Buffering Alone during Decoding

      1296
    • 23.6.2 When CROMST0 Status Register Bits are Set

      1296
    • 23.6.3 Link Blocks

      1297
    • 23.6.4 Stopping and Resuming CD-DSP Operation

      1297
    • 23.6.5 Note on Clearing the IREADY Flag

      1297
    • 23.6.6 Note on Stream Data Transfer (1)

      1298
    • 23.6.7 Note on Stream Data Transfer (2)

      1298
• Section 24 A/D Converter

  1299
  • 24.1 Features

    1299
  • 24.2 Input/Output Pins

    1301
  • 24.3 Register Descriptions

    1302
    • 24.3.1 A/D Data Registers A to H (ADDRA to ADDRH)

      1303
    • 24.3.2 A/D Control/Status Register (ADCSR)

      1304
  • 24.4 Operation

    1308
    • 24.4.1 Single Mode

      1308
    • 24.4.2 Multi Mode

      1311
    • 24.4.3 Scan Mode

      1313
    • 24.4.4 A/D Converter Activation by External Trigger or Multi-Function Timer Pulse Unit 2

      1316
    • 24.4.5 Input Sampling and A/D Conversion Time

      1316
    • 24.4.6 External Trigger Input Timing

      1319
  • 24.5 Interrupt Sources and DMA Transfer Request

    1320
  • 24.6 Definitions of A/D Conversion Accuracy

    1321
  • 24.7 Usage Notes

    1322
    • 24.7.1 Module Standby Mode Setting

      1322
    • 24.7.2 Setting Analog Input Voltage

      1322
    • 24.7.3 Notes on Board Design

      1322
    • 24.7.4 Processing of Analog Input Pins

      1323
    • 24.7.5 Permissible Signal Source Impedance

      1324
    • 24.7.6 Influences on Absolute Precision

      1325
    • 24.7.7 Note on Usage in Scan Mode and Multi Mode

      1325
• Section 25 NAND Flash Memory Controller

  1327
  • 25.1 Features

    1327
  • 25.2 Input/Output Pins

    1331
  • 25.3 Register Descriptions

    1332
    • 25.3.1 Common Control Register (FLCMNCR)

      1333
    • 25.3.2 Command Control Register (FLCMDCR)

      1337
    • 25.3.3 Command Code Register (FLCMCDR)

      1340
    • 25.3.4 Address Register (FLADR)

      1341
    • 25.3.5 Address Register 2 (FLADR2)

      1343
    • 25.3.6 Data Counter Register (FLDTCNTR)

      1344
    • 25.3.7 Data Register (FLDATAR)

      1345
    • 25.3.8 Interrupt DMA Control Register (FLINTDMACR)

      1346
    • 25.3.9 Ready Busy Timeout Setting Register (FLBSYTMR)

      1351
    • 25.3.10 Ready Busy Timeout Counter (FLBSYCNT)

      1352
    • 25.3.11 Data FIFO Register (FLDTFIFO)

      1353
    • 25.3.12 Control Code FIFO Register (FLECFIFO)

      1354
    • 25.3.13 Transfer Control Register (FLTRCR)

      1355
    • 25.3.14 Bus Hold Time Setting Register (FLHOLDCR)

      1356
    • 25.3.15 4-Symbol ECC Processing Result Register n (FL4ECCRESn) (n = 1 to 4)

      1357
    • 25.3.16 4-Symbol ECC Control Register (FL4ECCCR)

      1358
    • 25.3.17 4-Symbol ECC Error Count Register (FL4ECCCNT)

      1360
  • 25.4 Operation

    1362
    • 25.4.1 Access Sequence

      1362
    • 25.4.2 Operating Modes

      1362
    • 25.4.3 Register Setting Procedure

      1363
    • 25.4.4 Command Access Mode

      1364
    • 25.4.5 Sector Access Mode

      1367
    • 25.4.6 ECC Error Correction

      1372
    • 25.4.7 Status Read

      1377
  • 25.5 Interrupt Sources

    1378
  • 25.6 DMA Transfer Specifications

    1378
  • 25.7 Usage Notes

    1379
    • 25.7.1 External Bus Mastership Release Timing

      1379
    • 25.7.2 Writing to the Control-Code Area when 4-Symbol ECC Circuit is in Use

      1381
    • 25.7.3 Usage Notes for the SNAND Bit

      1382
• Section 26 USB 2.0 Host/Function Module

  1383
  • 26.1 Features

    1383
  • 26.2 Input/Output Pins

    1385
  • 26.3 Register Description

    1387
    • 26.3.1 System Configuration Control Register (SYSCFG)

      1390
    • 26.3.2 CPU Bus Wait Setting Register (BUSWAIT)

      1394
    • 26.3.3 System Configuration Status Register (SYSSTS)

      1395
    • 26.3.4 Device State Control Register (DVSTCTR)

      1396
    • 26.3.5 Test Mode Register (TESTMODE)

      1402
    • 26.3.6 DMA-FIFO Bus Configuration Registers (D0FBCFG, D1FBCFG)

      1405
    • 26.3.7 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO)

      1406
    • 26.3.8 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)

      1408
    • 26.3.9 FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR)

      1416
    • 26.3.10 Interrupt Enable Register 0 (INTENB0)

      1420
    • 26.3.11 Interrupt Enable Register 1 (INTENB1)

      1422
    • 26.3.12 BRDY Interrupt Enable Register (BRDYENB)

      1424
    • 26.3.13 NRDY Interrupt Enable Register (NRDYENB)

      1425
    • 26.3.14 BEMP Interrupt Enable Register (BEMPENB)

      1427
    • 26.3.15 SOF Output Configuration Register (SOFCFG)

      1428
    • 26.3.16 Interrupt Status Register 0 (INTSTS0)

      1430
    • 26.3.17 Interrupt Status Register 1 (INTSTS1)

      1435
    • 26.3.18 BRDY Interrupt Status Register (BRDYSTS)

      1441
    • 26.3.19 NRDY Interrupt Status Register (NRDYSTS)

      1443
    • 26.3.20 BEMP Interrupt Status Register (BEMPSTS)

      1445
    • 26.3.21 Frame Number Register (FRMNUM)

      1446
    • 26.3.22 (Frame Number Register (UFRMNUM)

      1449
    • 26.3.23 USB Address Register (USBADDR)

      1450
    • 26.3.24 USB Request Type Register (USBREQ)

      1451
    • 26.3.25 USB Request Value Register (USBVAL)

      1452
    • 26.3.26 USB Request Index Register (USBINDX)

      1453
    • 26.3.27 USB Request Length Register (USBLENG)

      1454
    • 26.3.28 DCP Configuration Register (DCPCFG)

      1455
    • 26.3.29 DCP Maximum Packet Size Register (DCPMAXP)

      1457
    • 26.3.30 DCP Control Register (DCPCTR)

      1458
    • 26.3.31 Pipe Window Select Register (PIPESEL)

      1468
    • 26.3.32 Pipe Configuration Register (PIPECFG)

      1469
    • 26.3.33 Pipe Buffer Setting Register (PIPEBUF)

      1476
    • 26.3.34 Pipe Maximum Packet Size Register (PIPEMAXP)

      1479
    • 26.3.35 Pipe Timing Control Register (PIPEPERI)

      1481
    • 26.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 9)

      1483
    • 26.3.37 PIPEn Transaction Counter Enable Registers (PIPEnTRE) (n = 1 to 5)

      1504
    • 26.3.38 PIPEn Transaction Counter Registers (PIPEnTRN) (n = 1 to 5)

      1506
    • 26.3.39 Device Address n Configuration Registers (DEVADDn) (n = 0 to A)

      1508
    • 26.3.40 USB AC Characteristics Switching Register 1 (USBACSWR1)

      1511
  • 26.4 Operation

    1512
    • 26.4.1 System Control and Oscillation Control

      1512
    • 26.4.2 Interrupt Functions

      1516
    • 26.4.3 Pipe Control

      1539
    • 26.4.4 FIFO Buffer Memory

      1549
    • 26.4.5 Control Transfers (DCP)

      1564
    • 26.4.6 Bulk Transfers (PIPE1 to PIPE5)

      1568
    • 26.4.7 Interrupt Transfers (PIPE6 to PIPE9)

      1570
    • 26.4.8 Isochronous Transfers (PIPE1 and PIPE2)

      1571
    • 26.4.9 SOF Interpolation Function

      1583
    • 26.4.10 Pipe Schedule

      1584
  • 26.5 Usage Notes

    1586
    • 26.5.1 Procedure for Setting the USB Transceiver

      1586
    • 26.5.2 Power Supply for USB Transceiver

      1586
• Section 27 Video Display Controller 3

  1587
  • 27.1 Overview

    1587
  • 27.2 Features

    1587
  • 27.3 Input/Output Pins

    1589
  • 27.4 Configuration

    1590
  • 27.5 Input Video Interface

    1592
    • 27.5.1 BT.601 Video Input

      1592
    • 27.5.2 BT.656 Video Input

      1593
  • 27.6 Functional Descriptions

    1596
    • 27.6.1 Video Display Function

      1596
    • 27.6.2 Video Recording Function

      1601
    • 27.6.3 Panel Control Signal Output Function

      1603
  • 27.7 Register Descriptions

    1606
    • 27.7.1 Video Operating Mode Register (VIDEO_MODE)

      1610
    • 27.7.2 Video Interrupt Control Register (VIDEO_INT_CNT)

      1614
    • 27.7.3 Video Input Timing Control Register (VIDEO_TIM_CNT)

      1617
    • 27.7.4 Valid Video Size Register (VIDEO_SIZE)

      1619
    • 27.7.5 Vertical Valid Video Start Position Register (VIDEO_VSTART)

      1620
    • 27.7.6 Horizontal Valid Video Start Position Register (VIDEO_HSTART)

      1621
    • 27.7.7 Timing Control Register 1 for Vertical Sync Signal for Video (VIDEO_VSYNC_TIM1)

      1623
    • 27.7.8 Video Storing Field Count Register (VIDEO_SAVE_NUM)

      1624
    • 27.7.9 Video Scaling and Correction Register (VIDEO_IMAGE_CNT)

      1625
    • 27.7.10 Video Base Address Register (VIDEO_BASEADR)

      1627
    • 27.7.11 Video Line Offset Register (VIDEO_LINE_OFFSET)

      1628
    • 27.7.12 Video Field Offset Register (VIDEO_FIELD_OFFSET)

      1629
    • 27.7.13 Video Line Buffer Count Register (VIDEO_LINEBUFF_NUM)

      1630
    • 27.7.14 Video Display and Recording Size Register (VIDEO_DISP_SIZE)

      1631
    • 27.7.15 Horizontal Video Display Position Register (VIDEO_DISP_HSTART)

      1632
    • 27.7.16 Graphics Block Control Registers (GRCMEN1 and GRCMEN2)

      1633
    • 27.7.17 Bus Control Registers (GRCBUSCNT1 and GRCBUSCNT2)

      1635
    • 27.7.18 Graphics Block Interrupt Control Registers (GRCINTCNT1 and GRCINTCNT2)

      1638
    • 27.7.19 Graphics Image Base Address Registers (GROPSADR1 and GROPSADR2)

      1639
    • 27.7.20 Graphics Image Size Registers (GROPSWH1 and GROPSWH2)

      1639
    • 27.7.21 Graphics Image Line Offset Registers (GROPSOFST1 and GROPSOFST2)

      1641
    • 27.7.22 Graphics Image Start Position Registers (GROPDPHV1 and GROPDPHV2)

      1642
    • 27.7.23 ( Control Area Size Registers (GROPEWH1 and GROPEWH2)

      1643
    • 27.7.24 ( Control Area Start Position Registers (GROPEDPHV1 and GROPEDPHV2)

      1644
    • 27.7.25 ( Control Registers (GROPEDPA1 and GROPEDPA2)

      1645
    • 27.7.26 Chroma-Key Control Registers (GROPCRKY0_1 and GROPCRKY0_2)

      1648
    • 27.7.27 Chroma-Key Color Registers (GROPCRKY1_1 and GROPCRKY1_2)

      1649
    • 27.7.28 Color Registers for Outside of Graphics Image Area (GROPBASERGB1 and GROPBASERGB2)

      1650
    • 27.7.29 SG Mode Register (SGMODE)

      1651
    • 27.7.30 Interrupt Output Control Register (SGINTCNT)

      1652
    • 27.7.31 Sync Signal Control Register (SYNCNT)

      1653
    • 27.7.32 Panel Clock Select Register (PANEL_CLKSEL)

      1655
    • 27.7.33 Sync Signal Size Register (SYN_SIZE)

      1657
    • 27.7.34 Vertical Sync Signal Timing Control Register (PANEL_VSYNC_TIM)

      1658
    • 27.7.35 Horizontal Sync Signal Timing Control Register (PANEL_HSYNC_TIM)

      1659
    • 27.7.36 Timing Control Register 2 for Vertical Sync Signal for Video (VIDEO_VSYNC_TIM2)

      1660
    • 27.7.37 Timing Control Register for Vertical Sync Signal for Graphics Image (GRA_VSYNC_TIM)

      1661
    • 27.7.38 AC Modulation Signal Toggle Line Count Register (AC_LINE_NUM)

      1662
    • 27.7.39 DE Area Size Register (DE_SIZE)

      1663
    • 27.7.40 DE Area Start Position Register (DE_START)

      1664
  • 27.8 Usage Notes

    1666
    • 27.8.1 Input Video Format Settings

      1666
    • 27.8.2 How to Use Video Recording Mode

      1667
    • 27.8.3 How to Use Video Display Mode

      1668
    • 27.8.4 How to Use Graphics Display

      1672
    • 27.8.5 How to Use Control Signal Output to Panel

      1675
  • 27.9 Interrupt Requests

    1676
  • 27.10 Usage Note

    1676
    • 27.10.1 The Procedure of Disabling the Video Receiving Block Operation

      1676
• Section 28 Sampling Rate Converter

  1677
  • 28.1 Features

    1677
  • 28.2 Register Descriptions

    1679
    • 28.2.1 Input Data Register (SRCID)

      1680
    • 28.2.2 Output Data Register (SRCOD)

      1681
    • 28.2.3 Input Data Control Register (SRCIDCTRL)

      1683
    • 28.2.4 Output Data Control Register (SRCODCTRL)

      1685
    • 28.2.5 Control Register (SRCCTRL)

      1687
    • 28.2.6 Status Register (SRCSTAT)

      1693
  • 28.3 Operation

    1698
    • 28.3.1 Initial Setting

      1698
    • 28.3.2 Data Input

      1699
    • 28.3.3 Data Output

      1701
  • 28.4 Interrupts

    1703
  • 28.5 Usage Notes

    1704
    • 28.5.1 Notes on Accessing Registers

      1704
    • 28.5.2 Notes on Flush Processing

      1704
    • 28.5.3 Notes on Using Two Channels at the Same Time

      1705
• Section 29 SD Host Interface

  1707
• Section 30 Decompression Unit

  1709
• Section 31 On-Chip RAM

  1711
  • 31.1 Features

    1711
  • 31.2 Usage Notes

    1715
    • 31.2.1 Page Conflict

      1715
    • 31.2.2 RAME and RAMWE Bits

      1715
    • 31.2.3 Data Retention

      1716
• Section 32 General Purpose I/O Ports

  1717
  • 32.1 Features

    1717
  • 32.2 Register Descriptions

    1726
    • 32.2.1 Port A I/O Register 0 (PAIOR0)

      1729
    • 32.2.2 Port A Data Registers 1, 0 (PADR1, PADR0)

      1729
    • 32.2.3 Port A Port Register 0 (PAPR0)

      1731
    • 32.2.4 Port B Control Registers 0 to 5 (PBCR0 to PBCR5)

      1731
    • 32.2.5 Port B I/O Registers 0, 1 (PBIOR0, PBIOR1)

      1741
    • 32.2.6 Port B Data Registers 0, 1 (PBDR0, PBDR1)

      1742
    • 32.2.7 Port B Port Registers 0, 1 (PBPR0, PBPR1)

      1744
    • 32.2.8 Port C Control Registers 0 to 2 (PCCR0 to PCCR2)

      1746
    • 32.2.9 Port C I/O Register 0 (PCIOR0)

      1749
    • 32.2.10 Port C Data Register 0 (PCDR0)

      1750
    • 32.2.11 Port C Port Register 0 (PCPR0)

      1752
    • 32.2.12 Port D Control Register 0 to 3 (PDCR0 to PDCR3)

      1753
    • 32.2.13 Port D I/O Register 0 (PDIOR0)

      1759
    • 32.2.14 Port D Port Registers 0 (PDDR0)

      1760
    • 32.2.15 Port D Port Registers 0 (PDPR0)

      1762
    • 32.2.16 Port E Control Registers 0, 1 (PECR0, PECR1)

      1763
    • 32.2.17 Port E I/O Register 0 (PEIOR0)

      1765
    • 32.2.18 Port E Data Register 0 (PEDR0)

      1765
    • 32.2.19 Port E Port Register 0 (PEPR0)

      1767
    • 32.2.20 Port F Control Register 0 to 3 (PFCR0 to PFCR3)

      1768
    • 32.2.21 Port F I/O Register 0 (PFIOR0)

      1774
    • 32.2.22 Port F Data Register 0 (PFDR0)

      1774
    • 32.2.23 Port F Port Register 0 (PFPR0)

      1776
    • 32.2.24 Port G Control Register 0 to 7 (PGCR0 to PGCR7)

      1777
    • 32.2.25 Port G I/O Registers 0, 1 (PGIOR0, PGIOR1)

      1787
    • 32.2.26 Port G Data Register 0, 1 (PGDR0, PGDR1)

      1787
    • 32.2.27 Port G Port Register 0, 1 (PGPR0, PGPR1)

      1790
    • 32.2.28 Port H Control Register 0, 1 (PHCR0, PHCR1)

      1792
    • 32.2.29 Port H Port Register 0 (PHPR0)

      1795
    • 32.2.30 Port J Control Register 0 to 2 (PJCR0 to PJCR2)

      1796
    • 32.2.31 Port J I/O register 0 (PJIOR0)

      1799
    • 32.2.32 Port J Data Register 0 (PJDR0)

      1800
    • 32.2.33 Port J Port Register 0 (PJPR0)

      1801
    • 32.2.34 Port K Control Register 0 to 2 (PKCR0 to PKCR2: Available Only in the SH7264 Group)

      1802
    • 32.2.35 Port K I/O Register 0 (PKIOR0: Available Only in the SH7264 Group)

      1806
    • 32.2.36 Port K Data Register 0 (PKDR0: Available Only in the SH7264 Group)

      1806
    • 32.2.37 Port K Port Register 0 (PKPR0: Available Only in the SH7264 Group)

      1808
  • 32.3 Usage Notes

    1808
    • 32.3.1 Notes on Output Function from PE0 to PE5

      1808
• Section 33 Power-Down Modes

  1809
  • 33.1 Features

    1809
    • 33.1.1 Power-Down Modes

      1809
  • 33.2 Register Descriptions

    1812
    • 33.2.1 Standby Control Register 1 (STBCR1)

      1813
    • 33.2.2 Standby Control Register 2 (STBCR2)

      1814
    • 33.2.3 Standby Control Register 3 (STBCR3)

      1815
    • 33.2.4 Standby Control Register 4 (STBCR4)

      1817
    • 33.2.5 Standby Control Register 5 (STBCR5)

      1820
    • 33.2.6 Standby Control Register 6 (STBCR6)

      1822
    • 33.2.7 Standby Control Register 7 (STBCR7)

      1824
    • 33.2.8 Standby Control Register 8 (STBCR8)

      1826
    • 33.2.9 Software Reset Control Register (SWRSTCR)

      1827
    • 33.2.10 System Control Register 1 (SYSCR1)

      1829
    • 33.2.11 System Control Register 2 (SYSCR2)

      1830
    • 33.2.12 System Control Register 3 (SYSCR3)

      1831
    • 33.2.13 System Control Register 4 (SYSCR4)

      1833
    • 33.2.14 System Control Register 5 (SYSCR5)

      1834
    • 33.2.15 On-Chip Data-Retention RAM Area Setting Register (RRAMKP)

      1836
    • 33.2.16 Deep Standby Control Register (DSCTR)

      1838
    • 33.2.17 Deep Standby Cancel Source Select Register (DSSSR)

      1839
    • 33.2.18 Deep Standby Cancel Edge Select Register (DSESR)

      1841
    • 33.2.19 Deep Standby Cancel Source Flag Register (DSFR)

      1843
    • 33.2.20 XTAL Crystal Oscillator Gain Control Register (XTALCTR)

      1845
  • 33.3 Operation

    1846
    • 33.3.1 Sleep Mode

      1846
    • 33.3.2 Software Standby Mode

      1847
    • 33.3.3 Software Standby Mode Application Example

      1850
    • 33.3.4 Deep Standby Mode

      1851
    • 33.3.5 Module Standby Function

      1857
    • 33.3.6 Adjustment of XTAL Crystal Oscillator Gain

      1857
  • 33.4 Usage Notes

    1858
    • 33.4.1 Usage Notes on Setting Registers

      1858
    • 33.4.2 Usage Notes when the Realtime Clock is not Used

      1858
• Section 34 User Debugging Interface

  1859
  • 34.1 Features

    1859
  • 34.2 Input/Output Pins

    1860
  • 34.3 Description of the Emulation Command Registers

    1861
    • 34.3.1 Bypass Register (SDBPR)

      1861
    • 34.3.2 Instruction Register (SDIR)

      1861
    • 34.3.3 Enable Register (SDENR)

      1863
  • 34.4 Operation

    1864
    • 34.4.1 TAP Controller

      1864
    • 34.4.2 Reset Configuration

      1865
    • 34.4.3 TDO Output Timing

      1865
    • 34.4.4 User Debugging Interface Reset

      1866
    • 34.4.5 User Debugging Interface Interrupt

      1866
  • 34.5 Usage Notes

    1867
• Section 35 Motor Control PWM Timer

  1869
  • 35.1 Features

    1869
  • 35.2 Input/Output Pins

    1871
  • 35.3 Register Descriptions

    1872
    • 35.3.1 PWM Control Register_n (PWCR_n) (n = 1, 2)

      1873
    • 35.3.2 PWM Polarity Register_n (PWPR_n) (n = 1, 2)

      1874
    • 35.3.3 PWM Counter_n (PWCNT_n) (n = 1, 2)

      1875
    • 35.3.4 PWM Cycle Register_n (PWCYR_n) (n = 1, 2)

      1875
    • 35.3.5 PWM Duty Registers_nA, nC, nE, nG (PWDTR_nA, PWDTR_nC, PWDTR_nE, PWDTR_nG) (n = 1, 2)

      1876
    • 35.3.6 PWM Buffer Registers_nA, nC, nE, nG (PWBFR_nA, PWBFR_nC, PWBFR_nE, PWBFR_nG) (n = 1, 2)

      1879
    • 35.3.7 PWM Buffer Transfer Control Register (PWBTCR)

      1880
  • 35.4 Bus Master Interface

    1881
    • 35.4.1 16-Bit Data Registers

      1881
    • 35.4.2 8-Bit Data Registers

      1881
  • 35.5 Operation

    1882
    • 35.5.1 PWM Operation

      1882
    • 35.5.2 Buffer Transfer Control

      1883
  • 35.6 Usage Note

    1884
    • 35.6.1 Conflict between Buffer Register Write and Compare Match

      1884
• Section 36 List of Registers

  1885
• Section 37 Electrical Characteristics

  2001
  • 37.4.1 Clock Timing

    2014
  • 37.4.2 Control Signal Timing

    2019
  • 37.4.3 Bus Timing

    2021
  • 37.4.4 Direct Memory Access Controller Timing

    2055
  • 37.4.5 Multi-Function Timer Pulse Unit 2 Timing

    2056
  • 37.4.6 Watchdog Timer Timing

    2057
  • 37.4.7 Serial Communication Interface with FIFO Timing

    2058
  • 37.4.8 Renesas Serial Peripheral Interface Timing

    2059
  • 37.4.9 I2C Bus Interface 3 Timing

    2063
  • 37.4.10 Serial Sound Interface Timing

    2065
  • 37.4.11 Serial I/O with FIFO Timing

    2067
  • 37.4.12 A/D Converter Timing

    2069
  • 37.4.13 NAND Type Flash Memory Controller Timing

    2070
  • 37.4.14 USB 2.0 Host/Function Module Timing

    2075
  • 37.4.15 Video Display Controller 3 Timing

    2078
  • 37.4.16 SD Host Interface Timing

    2080
  • 37.4.17 General Purpose I/O Ports Timing

    2081
  • 37.4.18 User Debugging Interface Timing

    2082
  • 37.4.19 Motor Control PWM Timer

    2084
  • 37.4.20 AC Characteristics Measurement Conditions

    2085
• Section 38 States and Handling of Pins

  2087
• Appendix

  2103
• Main Revisions for This Edition

  2105
• Index

  2137
• Colophon

  2149
• Address List

  2150
• Back Cover

  2152