BenutzerhandbuchInhaltsverzeichnisTable of Contents3Preface61 Introduction91.1 Purpose of the Peripheral91.2 Features91.3 Functional Block Diagram91.4 Industry Standard(s) Compliance Statement102 Peripheral Architecture112.1 Clock Control112.2 Memory Map112.3 Signal Descriptions112.4 Protocol Description(s)132.4.1 Mode Register Set (MRS and EMRS)142.4.2 Refresh Mode142.4.3 Activation (ACTV)152.4.4 Deactivation (DCAB and DEAC)162.4.5 READ Command172.4.6 Write (WRT) Command182.5 Memory Width and Byte Alignment182.6 Address Mapping192.7 DDR2 Memory Controller Interface222.7.1 Command Ordering and Scheduling, Advanced Concept232.7.2 Command Starvation242.7.3 Possible Race Condition252.8 Refresh Scheduling252.9 Self-Refresh Mode262.10 Reset Considerations262.11 DDR2 SDRAM Memory Initialization272.11.1 DDR2 SDRAM Device Mode Register Configuration Values272.11.2 DDR2 SDRAM Initialization After Reset282.11.3 DDR2 SDRAM Initialization After Register Configuration282.12 Interrupt Support282.13 EDMA Event Support282.14 Emulation Considerations283 Using the DDR2 Memory Controller293.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM293.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications333.2.1 Programming the SDRAM Configuration Register (SDCFG)333.2.2 Programming the SDRAM Refresh Control Register (SDRFC)333.2.3 Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)343.2.4 Configuring the DDR2 Memory Controller Control Register (DMCCTL)354 DDR2 Memory Controller Registers364.1 Module ID and Revision Register (MIDR)374.2 DDR2 Memory Controller Status Register (DMCSTAT)374.3 SDRAM Configuration Register (SDCFG)384.4 SDRAM Refresh Control Register (SDRFC)404.5 SDRAM Timing 1 Register (SDTIM1)414.6 SDRAM Timing 2 Register (SDTIM2)434.7 Burst Priority Register (BPRIO)444.8 DDR2 Memory Controller Control Register (DMCCTL)45Appendix A Revision History46Größe: 413 KBSeiten: 47Language: EnglishHandbuch öffnen