Benutzerhandbuch für Texas Instruments DM648 DSP

Inhaltsverzeichnis

• Table of Contents

  3
• Preface

  6
• 1 Introduction

  9
  • 1.1 Purpose of the Peripheral

    9
  • 1.2 Features

    9
  • 1.3 Functional Block Diagram

    9
  • 1.4 Industry Standard(s) Compliance Statement

    10
• 2 Peripheral Architecture

  11
  • 2.1 Clock Control

    11
  • 2.2 Memory Map

    11
  • 2.3 Signal Descriptions

    11
  • 2.4 Protocol Description(s)

    13
    • 2.4.1 Mode Register Set (MRS and EMRS)

      14
    • 2.4.2 Refresh Mode

      14
    • 2.4.3 Activation (ACTV)

      15
    • 2.4.4 Deactivation (DCAB and DEAC)

      16
    • 2.4.5 READ Command

      17
    • 2.4.6 Write (WRT) Command

      18
  • 2.5 Memory Width and Byte Alignment

    18
  • 2.6 Address Mapping

    19
  • 2.7 DDR2 Memory Controller Interface

    22
    • 2.7.1 Command Ordering and Scheduling, Advanced Concept

      23
    • 2.7.2 Command Starvation

      24
    • 2.7.3 Possible Race Condition

      25
  • 2.8 Refresh Scheduling

    25
  • 2.9 Self-Refresh Mode

    26
  • 2.10 Reset Considerations

    26
  • 2.11 DDR2 SDRAM Memory Initialization

    27
    • 2.11.1 DDR2 SDRAM Device Mode Register Configuration Values

      27
    • 2.11.2 DDR2 SDRAM Initialization After Reset

      28
    • 2.11.3 DDR2 SDRAM Initialization After Register Configuration

      28
  • 2.12 Interrupt Support

    28
  • 2.13 EDMA Event Support

    28
  • 2.14 Emulation Considerations

    28
• 3 Using the DDR2 Memory Controller

  29
  • 3.1 Connecting the DDR2 Memory Controller to DDR2 SDRAM

    29
  • 3.2 Configuring DDR2 Memory Controller Registers to Meet DDR2 SDRAM Specifications

    33
    • 3.2.1 Programming the SDRAM Configuration Register (SDCFG)

      33
    • 3.2.2 Programming the SDRAM Refresh Control Register (SDRFC)

      33
    • 3.2.3 Configuring SDRAM Timing Registers (SDTIM1 and SDTIM2)

      34
    • 3.2.4 Configuring the DDR2 Memory Controller Control Register (DMCCTL)

      35
• 4 DDR2 Memory Controller Registers

  36
  • 4.1 Module ID and Revision Register (MIDR)

    37
  • 4.2 DDR2 Memory Controller Status Register (DMCSTAT)

    37
  • 4.3 SDRAM Configuration Register (SDCFG)

    38
  • 4.4 SDRAM Refresh Control Register (SDRFC)

    40
  • 4.5 SDRAM Timing 1 Register (SDTIM1)

    41
  • 4.6 SDRAM Timing 2 Register (SDTIM2)

    43
  • 4.7 Burst Priority Register (BPRIO)

    44
  • 4.8 DDR2 Memory Controller Control Register (DMCCTL)

    45
• Appendix A Revision History

  46