Benutzerhandbuch für Texas Instruments TMS320C6712D

Inhaltsverzeichnis

• SPRS293A - TMS320C6712D

  1
• features

  1
• Table of Contents

  2
• REVISION HISTORY

  3
• GDP and ZDP BGA package (bottom view)

  5
• description

  6
• device characteristics

  7
• device compatibility

  8
• functional block and CPU (DSP core) diagram

  9
• CPU (DSP core) description

  10
• memory map summary

  12
• peripheral register descriptions

  13
• signal groups description

  18
• DEVICE CONFIGURATIONS

  20
  • device configurations at device reset

    20
  • DEVCFG register description

    22
• TERMINAL FUNCTIONS

  23
  • Terminal Functions

    24
• development support

  36
  • Software Development Tools:

    36
  • Hardware Development Tools:

    36
• device support

  37
  • device and development-support tool nomenclature

    37
    • TMX

      37
    • TMP

      37
    • TMS

      37
    • TMDX

      37
    • TMDS

      37
  • documentation support

    39
• CPU CSR register description

  40
• cache configuration (CCFG) register description

  42
• interrupt sources and interrupt selector

  43
• EDMA module and EDMA selector

  44
  • ESEL0 Register (0x01A0 FF00)

    45
  • ESEL1 Register (0x01A0 FF04)

    45
  • ESEL3 Register (0x01A0 FF0C)

    45
• PLL and PLL controller

  46
  • PLLCSR Register (0x01B7 C100)

    49
  • PLLM Register (0x01B7 C110)

    50
  • Table 29. PLL Multiplier Control Register (PLLM)

    50
  • PLLDIV0, PLLDIV1, PLLDIV2, and PLLDIV3 Registers

    51
  • OSCDIV1 Register (0x01B7 C124)

    52
• general-purpose input/output (GPIO)

  53
• power-down mode logic

  54
  • triggering, wake-up, and effects

    54
• power-supply sequencing

  56
  • system-level design considerations

    56
  • power-supply design considerations

    56
• power-supply decoupling

  57
• IEEE 1149.1 JTAG compatibility statement

  58
• EMIF device speed

  59
• EMIF big endian mode correctness

  60
• bootmode

  60
• reset

  60
• absolute maximum ratings over operating case temperature range (unless otherwise noted)†

  61
• recommended operating conditions

  61
• electrical characteristics over recommended ranges of supply voltage and operating case temperature† ( unless otherwise noted)

  62
• PARAMETER MEASUREMENT INFORMATION

  63
  • signal transition levels

    63
  • AC transient rise/fall time specifications

    64
  • timing parameters and board routing analysis

    65
• INPUT AND OUTPUT CLOCKS

  67
  • timing requirements for CLKIN†‡§ (see Figure 21)

    67
  • switching characteristics over recommended operating conditions for CLKOUT2‡§ (see Figure 22)

    67
  • switching characteristics over recommended operating conditions for CLKOUT3†‡ ( see Figure 23)

    68
  • timing requirements for ECLKIN§ (see Figure 24)

    68
  • switching characteristics over recommended operating conditions for ECLKOUT†‡§ (see Figure 25)

    69
• ASYNCHRONOUS MEMORY TIMING

  70
  • timing requirements for asynchronous memory cycles†‡ (see Figure 26-Figure 27)

    70
  • switching characteristics over recommended operating conditions for asynchronous memory cycles‡§¶ (see Figure 26-Figure 27)

    70
• SYNCHRONOUS-BURST MEMORY TIMING

  73
  • timing requirements for synchronous-burst SRAM cycles† (see Figure 28)

    73
  • switching characteristics over recommended operating conditions for synchronous-burst SRAM cycles†‡ ( see Figure 28 and Figure 29)

    73
• SYNCHRONOUS DRAM TIMING

  75
  • timing requirements for synchronous DRAM cycles† (see Figure 30)

    75
  • switching characteristics over recommended operating conditions for synchronous DRAM cycles†‡ ( see Figure 30- Figure 36)

    75
• HOLD\/HOLDA\ TIMING

  81
  • timing requirements for the HOLD\/HOLDA\ cycles† (see Figure 37)

    81
  • switching characteristics over recommended operating conditions for the HOLD\/HOLDA\ cycles†‡ ( see Figure 37)

    81
• BUSREQ TIMING

  82
  • switching characteristics over recommended operating conditions for the BUSREQ cycles ( see Figure 38)

    82
• RESET TIMING

  83
  • timing requirements for reset†‡ (see Figure 39)

    83
  • switching characteristics over recommended operating conditions during reset¶ (see Figure 39)

    83
• EXTERNAL INTERRUPT TIMING

  85
  • timing requirements for external interrupts† (see Figure 40)

    85
• MULTICHANNEL BUFFERED SERIAL PORT TIMING

  86
  • timing requirements for McBSP†‡ ( see Figure 41)

    86
  • switching characteristics over recommended operating conditions for McBSP†‡ (see Figure 41)

    87
  • timing requirements for FSR when GSYNC = 1 (see Figure 42)

    89
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 43)

    89
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ ( see Figure 43)

    90
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ (see Figure 44)

    90
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 0†‡ ( see Figure 44)

    91
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ (see Figure 45)

    92
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 1†‡ ( see Figure 45)

    92
  • timing requirements for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ (see Figure 46)

    93
  • switching characteristics over recommended operating conditions for McBSP as SPI master or slave: CLKSTP = 11b, CLKXP = 1†‡ ( see Figure 46)

    93
• TIMER TIMING

  95
  • timing requirements for timer inputs† (see Figure 47)

    95
  • switching characteristics over recommended operating conditions for timer outputs† ( see Figure 47)

    95
• GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORT TIMING

  96
  • timing requirements for GPIO inputs†‡ (see Figure 48)

    96
  • switching characteristics over recommended operating conditions for GPIO outputs†§ (see Figure 48)

    96
• JTAG TEST-PORT TIMING

  97
  • timing requirements for JTAG test port (see Figure 49)

    97
  • switching characteristics over recommended operating conditions for JTAG test port ( see Figure 49)

    97
• MECHANICAL DATA

  98
  • package thermal resistance characteristics

    98
  • thermal resistance characteristics (S-PBGA package) for GDP

    98
  • thermal resistance characteristics (S-PBGA package) for ZDP

    98
  • packaging information

    98