Benutzerhandbuch für Texas Instruments TMS320DM355

Inhaltsverzeichnis

• 1 TMS320DM355 Digital Media System-on-Chip (DMSoC)

  1
  • 1.1 Features

    1
  • 1.2 Description

    3
  • 1.3 Functional Block Diagram

    4
• Table of Contents

  5
• 2 Device Overview

  6
  • 2.1 Device Characteristics

    6
  • 2.2 Memory Map Summary

    7
  • 2.3 Pin Assignments

    9
    • 2.3.1  Pin Map (Bottom View)

      9
  • 2.4 Pin Functions

    13
    • 2.4.1 Image Data Input - Video Processing Front End

      13
    • 2.4.2 Image Data Output - Video Processing Back End (VPBE)

      15
    • 2.4.3 Asynchronous External Memory Interface (AEMIF)

      18
    • 2.4.4 DDR Memory Interface

      20
    • 2.4.5 GPIO

      22
    • 2.4.6 Multi-Media Card/Secure Digital (MMC/SD) Interfaces

      28
    • 2.4.7 Universal Serial Bus (USB) Interface

      29
    • 2.4.8 Audio Interfaces

      29
    • 2.4.9 UART Interface

      30
    • 2.4.10 I2C Interface

      31
    • 2.4.11 Serial Interface

      31
    • 2.4.12 Clock Interface

      32
    • 2.4.13 Real Time Output (RTO) Interface

      33
    • 2.4.14 Pulse Width Modulator (PWM) Interface

      33
    • 2.4.15 System Configuration Interface

      34
    • 2.4.16 Emulation

      35
  • 2.5 Pin List

    36
  • 2.6 Device Support

    55
    • 2.6.1 Development Tools

      55
    • 2.6.2  Device Nomenclature

      55
    • 2.6.3 Device Documentation

      56
• 3 Detailed Device Description

  59
  • 3.1 ARM Subsystem Overview

    59
    • 3.1.1 Components of the ARM Subsystem

      59
  • 3.2 ARM926EJ-S RISC CPU

    60
    • 3.2.1 CP15

      61
    • 3.2.2 MMU

      61
    • 3.2.3 Caches and Write Buffer

      61
    • 3.2.4 Tightly Coupled Memory (TCM)

      62
    • 3.2.5 Advanced High-performance Bus (AHB)

      62
    • 3.2.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

      62
  • 3.3  Memory Mapping

    62
    • 3.3.1 ARM Internal Memories

      62
    • 3.3.2 External Memories

      63
    • 3.3.3 Peripherals

      63
  • 3.4 ARM Interrupt Controller (AINTC)

    63
    • 3.4.1 Interrupt Mapping

      63
  • 3.5 Device Clocking

    65
    • 3.5.1 Overview

      65
    • 3.5.2 Supported Clocking Configurations for DM355-216

      67
    • 3.5.3 Supported Clocking Configurations for DM355-270

      69
    • 3.5.4  Peripheral Clocking Considerations

      71
  • 3.6 PLL Controller (PLLC)

    73
    • 3.6.1 PLL Controller Module

      73
    • 3.6.2  PLLC1

      74
    • 3.6.3 PLLC2

      76
  • 3.7 Power and Sleep Controller (PSC)

    77
  • 3.8 System Control Module

    77
  • 3.9 Pin Multiplexing

    78
    • 3.9.1 Hardware Controlled Pin Multiplexing

      78
    • 3.9.2 Software Controlled Pin Multiplexing

      79
  • 3.10 Device Reset

    79
  • 3.11 Default Device Configurations

    80
    • 3.11.1 Device Configuration Pins

      80
    • 3.11.2 PLL Configuration

      81
    • 3.11.3 Power Domain and Module State Configuration

      81
    • 3.11.4 ARM Boot Mode Configuration

      83
    • 3.11.5 AEMIF Configuration

      83
  • 3.12 Device Boot Modes

    83
    • 3.12.1 Boot Modes Overview

      84
  • 3.13 Power Management

    85
  • 3.14 64-Bit Crossbar Architecture

    87
    • 3.14.1 Crossbar Connections

      87
    • 3.14.2 EDMA Controller

      87
  • 3.15 MPEG/JPEG Overview

    90
• 4 Device Operating Conditions

  91
  • 4.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted)

    91
  • 4.2 Recommended Operating Conditions

    92
  • 4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)

    93
• 5  Peripheral Information and Electrical Specifications

  94
  • 5.1  Parameter Information Device-Specific Information

    94
    • 5.1.1  Signal Transition Levels

      94
    • 5.1.2  Timing Parameters and Board Routing Analysis

      95
  • 5.2 Recommended Clock and Control Signal Transition Behavior

    96
  • 5.3 Power Supplies

    96
    • 5.3.1 Power-Supply Sequencing

      97
  • 5.4 Reset

    98
    • 5.4.1  Reset Electrical Data/Timing

      98
  • 5.5 Oscillators and Clocks

    99
    • 5.5.1 MXI1 (24-MHz) Oscillator

      99
    • 5.5.2 MXI2 (27-MHz) Oscillator (optional oscillator)

      100
    • 5.5.3  Clock PLL Electrical Data/Timing (Input and Output Clocks)

      101
  • 5.6 General-Purpose Input/Output (GPIO)

    104
    • 5.6.1  GPIO Peripheral Input/Output Electrical Data/Timing

      104
    • 5.6.2  GPIO Peripheral External Interrupts Electrical Data/Timing

      105
  • 5.7 External Memory Interface (EMIF)

    106
    • 5.7.1 Asynchronous EMIF (AEMIF)

      106
    • 5.7.2 DDR2 Memory Controller

      112
  • 5.8 MMC/SD

    113
    • 5.8.1 MMC/SD Electrical Data/Timing

      113
  • 5.9 Video Processing Sub-System (VPSS) Overview

    115
    • 5.9.1 Video Processing Front-End (VPFE)

      115
    • 5.9.2 Video Processing Back-End (VPBE)

      120
  • 5.10  USB 2.0

    127
    • 5.10.1 USB2.0 Electrical Data/Timing

      127
  • 5.11  Universal Asynchronous Receiver/Transmitter (UART)

    129
    • 5.11.1 UART Electrical Data/Timing

      129
  • 5.12  Serial Port Interface (SPI)

    131
    • 5.12.1 SPI Electrical Data/Timing

      131
  • 5.13 Inter-Integrated Circuit (I2C)

    134
    • 5.13.1  I2C Electrical Data/Timing

      135
  • 5.14 Audio Serial Port (ASP)

    137
    • 5.14.1  ASP Electrical Data/Timing

      138
  • 5.15 Timer

    144
    • 5.15.1  Timer Electrical Data/Timing

      144
  • 5.16  Pulse Width Modulator (PWM)

    145
    • 5.16.1 PWM0/1/2/3 Electrical/Timing Data

      145
  • 5.17  Real Time Out (RTO)

    147
    • 5.17.1 RTO Electrical/Timing Data

      147
  • 5.18 IEEE 1149.1 JTAG

    148
    • 5.18.1  JTAG Test-Port Electrical Data/Timing

      149
• 6 Revision History

  151
• 7 Mechanical Data

  153
  • 7.1 Thermal Data for ZCE

    153
  • 7.1.1 Packaging Information

    153