Benutzerhandbuch für Texas TMS320C67X/C67X+ DSP

Inhaltsverzeichnis

• Title Page - SPRU733

  1
• IMPORTANT NOTICE

  2
• Read This First

  3
  • About This Manual

    3
  • Notational Conventions

    3
  • Related Documentation From Texas Instruments

    3
  • Trademarks

    4
• Contents

  5
• Figures

  12
• Tables

  14
• Examples

  17
• Chapter 1: Introduction

  18
  • 1.1 TMS320 DSP Family Overview

    19
  • 1.2 TMS320C6000 DSP Family Overview

    19
  • 1.3 TMS320C67x DSP Features and Options

    21
  • 1.4 TMS320C67x DSP Architecture

    24
    • 1.4.1 Central Processing Unit (CPU)

      25
    • 1.4.2 Internal Memory

      25
    • 1.4.3 Memory and Peripheral Options

      25
• Chapter 2: CPU Data Paths and Control

  27
  • 2.1 Introduction

    28
  • 2.2 General-Purpose Register Files

    28
  • 2.3 Functional Units

    31
  • 2.4 Register File Cross Paths

    32
  • 2.5 Memory, Load, and Store Paths

    32
  • 2.6 Data Address Paths

    33
  • 2.7 Control Register File

    33
    • 2.7.1 Register Addresses for Accessing the Control Registers

      34
    • 2.7.2 Pipeline/Timing of Control Register Accesses

      35
    • 2.7.3 Addressing Mode Register (AMR)

      36
    • 2.7.4 Control Status Register (CSR)

      39
    • 2.7.5 Interrupt Clear Register (ICR)

      42
    • 2.7.6 Interrupt Enable Register (IER)

      43
    • 2.7.7 Interrupt Flag Register (IFR)

      44
    • 2.7.8 Interrupt Return Pointer Register (IRP)

      45
    • 2.7.9 Interrupt Set Register (ISR)

      46
    • 2.7.10 Interrupt Service Table Pointer Register (ISTP)

      47
    • 2.7.11 Nonmaskable Interrupt (NMI) Return Pointer Register (NRP)

      48
    • 2.7.12 E1 Phase Program Counter (PCE1)

      48
  • 2.8 Control Register File Extensions

    49
    • 2.8.1 Floating-Point Adder Configuration Register (FADCR)

      49
    • 2.8.2 Floating-Point Auxiliary Configuration Register (FAUCR)

      53
    • 2.8.3 Floating-Point Multiplier Configuration Register (FMCR)

      57
• Chapter 3: Instruction Set

  61
  • 3.1 Instruction Operation and Execution Notations

    62
  • 3.2 Instruction Syntax and Opcode Notations

    67
  • 3.3 Overview of IEEE Standard Single- and Double-Precision Formats

    69
  • 3.4 Delay Slots

    74
  • 3.5 Parallel Operations

    76
    • 3.5.1 Example Parallel Code

      78
    • 3.5.2 Branching Into the Middle of an Execute Packet

      78
  • 3.6 Conditional Operations

    79
  • 3.7 Resource Constraints

    80
    • 3.7.1 Constraints on Instructions Using the Same Functional Unit

      80
    • 3.7.2 Constraints on the Same Functional Unit Writing in the Same Instruction Cycle

      80
    • 3.7.3 Constraints on Cross Paths (1X and 2X)

      81
    • 3.7.4 Constraints on Loads and Stores

      82
    • 3.7.5 Constraints on Long (40-Bit) Data

      83
    • 3.7.6 Constraints on Register Reads

      84
    • 3.7.7 Constraints on Register Writes

      85
    • 3.7.8 Constraints on Floating-Point Instructions

      86
  • 3.8 Addressing Modes

    90
    • 3.8.1 Linear Addressing Mode

      90
      • 3.8.1.1 LD and ST Instructions

        90
      • 3.8.1.2 ADDA and SUBA Instructions

        90
    • 3.8.2 Circular Addressing Mode

      91
      • 3.8.2.1 LD and ST Instructions

        91
      • 3.8.2.2 ADDA and SUBA Instructions

        92
    • 3.8.3 Syntax for Load/Store Address Generation

      92
  • 3.9 Instruction Compatibility

    94
  • 3.10 Instruction Descriptions

    94
    • Example

      95
    • ABS

      98
    • ABSDP

      100
    • ABSSP

      102
    • ADD

      104
    • ADDAB

      108
    • ADDAD

      110
    • ADDAH

      112
    • ADDAW

      114
    • ADDDP

      116
    • ADDK

      119
    • ADDSP

      120
    • ADDU

      123
    • ADD2

      125
    • AND

      127
    • B displacement

      129
    • B register

      131
    • B IRP

      133
    • B NRP

      135
    • CLR

      137
    • CMPEQ

      140
    • CMPEQDP

      142
    • CMPEQSP

      144
    • CMPGT

      146
    • CMPGT

      148
    • CMPGTDP

      149
    • CMPGTSP

      151
    • CMPGTU

      153
    • CMPLT

      155
    • CMPLTDP

      158
    • CMPLTSP

      160
    • CMPLTU

      162
    • DPINT

      164
    • DPSP

      166
    • DPTRUNC

      168
    • EXT

      170
    • EXTU

      173
    • IDLE

      176
    • INTDP

      177
    • INTDPU

      179
    • INTSP

      181
    • INTSPU

      182
    • LDB(U)

      183
    • LDB(U)

      186
    • LDDW

      188
    • LDH(U)

      191
    • LDH(U)

      194
    • LDW

      196
    • LDW

      199
    • LMBD

      201
    • MPY

      203
    • MPYDP

      205
    • MPYH

      207
    • MPYHL

      209
    • MPYHLU

      211
    • MPYHSLU

      212
    • MPYHSU

      213
    • MPYHU

      214
    • MPYHULS

      215
    • MPYHUS

      216
    • MPYI

      217
    • MPYID

      219
    • MPYLH

      221
    • MPYLHU

      223
    • MPYLSHU

      224
    • MPYLUHS

      225
    • MPYSP

      226
    • MPYSPDP

      228
    • MPYSP2DP

      230
    • MPYSU

      232
    • MPYU

      234
    • MPYUS

      236
    • MV

      238
    • MVC

      240
    • MVK

      243
    • MVKH/MVKLH

      245
    • MVKL

      247
    • NEG

      249
    • NOP

      250
    • NORM

      252
    • NOT

      254
    • OR

      255
    • RCPDP

      257
    • RCPSP

      259
    • RSQRDP

      261
    • RSQRSP

      263
    • SADD

      265
    • SAT

      268
    • SET

      270
    • SHL

      273
    • SHR

      275
    • SHRU

      277
    • SMPY

      279
    • SMPYH

      281
    • SMPYHL

      282
    • SMPYLH

      284
    • SPDP

      286
    • SPINT

      288
    • SPTRUNC

      290
    • SSHL

      292
    • SSUB

      294
    • STB

      296
    • STB

      298
    • STH

      300
    • STH

      303
    • STW

      305
    • STW

      307
    • SUB

      309
    • SUBAB

      313
    • SUBAH

      315
    • SUBAW

      316
    • SUBC

      318
    • SUBDP

      320
    • SUBSP

      323
    • SUBU

      326
    • SUB2

      328
    • XOR

      330
    • ZERO

      332
• Chapter4: Pipeline

  333
  • 4.1 Pipeline Operation Overview

    334
    • 4.1.1 Fetch

      334
    • 4.1.2 Decode

      335
    • 4.1.3 Execute

      337
    • 4.1.4 Pipeline Operation Summary

      338
  • 4.2 Pipeline Execution of Instruction Types

    344
    • 4.2.1 Single-Cycle Instructions

      348
    • 4.2.2 16 x 16-Bit Multiply Instructions

      349
    • 4.2.3 Store Instructions

      350
    • 4.2.4 Load Instructions

      352
    • 4.2.5 Branch Instructions

      354
    • 4.2.6 Two-Cycle DP Instructions

      356
    • 4.2.7 Four-Cycle Instructions

      357
    • 4.2.8 INTDP Instruction

      358
    • 4.2.9 DP Compare Instructions

      359
    • 4.2.10 ADDDP/SUBDP Instructions

      360
    • 4.2.11 MPYI Instruction

      361
    • 4.2.12 MPYID Instruction

      362
    • 4.2.13 MPYDP Instruction

      363
    • 4.2.14 MPYSPDP Instruction

      364
    • 4.2.15 MPYSP2DP Instruction

      365
  • 4.3 Functional Unit Constraints

    365
    • 4.3.1 .S-Unit Constraints

      366
    • 4.3.2 .M-Unit Constraints

      372
    • 4.3.3 .L-Unit Constraints

      380
    • 4.3.4 .D-Unit Instruction Constraints

      384
  • 4.4 Performance Considerations

    388
    • 4.4.1 Pipeline Operation With Multiple Execute Packets in a Fetch Packet

      388
    • 4.4.2 Multicycle NOPs

      390
    • 4.4.3 Memory Considerations

      392
      • 4.4.3.1 Memory Stalls

        393
      • 4.4.3.2 Memory Bank Hits

        394
• Chapter 5: Interrupts

  396
  • 5.1 Overview

    397
    • 5.1.1 Types of Interrupts and Signals Used

      397
      • 5.1.1.1 Reset (RESET)

        398
      • 5.1.1.2 Nonmaskable Interrupt (NMI)

        399
      • 5.1.1.3 Maskable Interrupts (INT4-INT15)

        399
      • 5.1.1.4 Interrupt Acknowledgment (IACK) and Interrupt Number (INUMn)

        400
    • 5.1.2 Interrupt Service Table (IST)

      401
      • 5.1.2.1 Interrupt Service Fetch Packet (ISFP)

        402
      • 5.1.2.2 Interrupt Service Table Pointer (ISTP)

        404
    • 5.1.3 Summary of Interrupt Control Registers

      405
  • 5.2 Globally Enabling and Disabling Interrupts

    406
  • 5.3 Individual Interrupt Control

    408
    • 5.3.1 Enabling and Disabling Interrupts

      408
    • 5.3.2 Status of Interrupts

      409
    • 5.3.3 Setting and Clearing Interrupts

      409
    • 5.3.4 Returning From Interrupt Servicing

      410
      • 5.3.4.1 CPU State After RESET

        410
      • 5.3.4.2 Returning From Nonmaskable Interrupts

        410
      • 5.3.4.3 Returning From Maskable Interrupts

        410
  • 5.4 Interrupt Detection and Processing

    411
    • 5.4.1 Setting the Nonreset Interrupt Flag

      411
    • 5.4.2 Conditions for Processing a Nonreset Interrupt

      411
    • 5.4.3 Actions Taken During Nonreset Interrupt Processing

      413
    • 5.4.4 Setting the RESET Interrupt Flag

      414
    • 5.4.5 Actions Taken During RESET Interrupt Processing

      415
  • 5.5 Performance Considerations

    416
    • 5.5.1 General Performance

      416
    • 5.5.2 Pipeline Interaction

      416
  • 5.6 Programming Considerations

    417
    • 5.6.1 Single Assignment Programming

      417
    • 5.6.2 Nested Interrupts

      418
    • 5.6.3 Manual Interrupt Processing

      420
    • 5.6.4 Traps

      421
• Appendix A: Instruction Compatibility

  422
• Appendix B: Mapping Between Instruction and Functional Unit

  428
• Appendix C: .D Unit Instructions and Opcode Maps

  434
  • C.1 Instructions Executing in the .D Functional Unit

    435
  • C.2 Opcode Map Symbols and Meanings

    436
  • C.3 32-Bit Opcode Maps

    438
• Appendix D: .L Unit Instructions and Opcode Maps

  439
  • D.1 Instructions Executing in the .L Functional Unit

    440
  • D.2 Opcode Map Symbols and Meanings

    441
  • D.3 32-Bit Opcode Maps

    442
• Appendix E: .M Unit Instructions and Opcode Maps

  443
  • E.1 Instructions Executing in the .M Functional Unit

    444
  • E.2 Opcode Map Symbols and Meanings

    445
  • E.3 32-Bit Opcode Maps

    446
• Appendix F: .S Unit Instructions and Opcode Maps

  447
  • F.1 Instructions Executing in the .S Functional Unit

    448
  • F.2 Opcode Map Symbols and Meanings

    449
  • F.3 32-Bit Opcode Maps

    450
• Appendix G: No Unit Specified Instructions and Opcode Maps

  452
  • G.1 Instructions Executing With No Unit Specified

    453
  • G.2 Opcode Map Symbols and Meanings

    453
  • G.3 32-Bit Opcode Maps

    454
• Index

  455
  • A

    455
  • B

    456
  • C

    456
  • D

    458
  • E

    458
  • F

    458
  • G

    458
  • H

    458
  • I

    458
  • L

    460
  • M

    460
  • N

    462
  • O

    462
  • P

    462
  • R

    463
  • S

    464
  • T

    465
  • U

    465
  • V

    465
  • X

    465
  • Z

    465