Panasonic MN101C77C User Manual
Chapter 14 Automatic Transfer Controller
Control Registers
XIV - 7
13
Figure 14-2-3 ATC1 Transfer Data Counter (AT1TRC : x'03FD2', R/W)
ATC1 Control Register 1 (AT1CNT1)
AT1IR2
AT1IR1 AT1IR0
(At reset : - - -
x x x x x
)
-
AT1IR3
AT1IR3 AT1IR2 AT1IR1
External interrupt 0
External interrupt 1
Serial interface 0 interrupt
Reserved
Reserved
Serial interface 1 interrupt
(Disable)
Serial interface 3 interrupt
Serial interface 3 interrupt
A/D interrupt
Timer 7 capture trigger
External interrupt 2
External interrupt 3
External interrupt 3
Serial interface 4 interrupt
Timer 1 interrupt
Timer 7 interrupt
Software initialization
AT1IR0
ATC1 trigger
factor settings
factor settings
-
-
BTSTP
BTSTP
Burst transfer stop enable
0
1
Burst transfer stop disable
Burst transfer stop enable
(Transfer stops when external interrupt 0
occurs.)
occurs.)
AT1CNT1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
2
4
5
6
7
3
Figure 14-2-2 ATC1 Control Register 1 (AT1CNT1 : x'03FD1', R/W)
ATC1 Transfer Counter (AT1TRC)
AT1TRC
AT1TRC7
AT1TRC2 AT1TRC1 AT1TRC0
(At reset :
x x x x x x x x
)
AT1TRC6 AT1TRC5 AT1TRC4 AT1TRC3
AT1TRC7 to 0 ATC1 Transfer Data Count Setting
· For transfer modes 0 to D, set this register to the number of
ATC activations. The register decrements by 1 after every
ATC1 activation. When the count reaches x'00', an ATC1
interrupt occurs and the transfer ends.
ATC activations. The register decrements by 1 after every
ATC1 activation. When the count reaches x'00', an ATC1
interrupt occurs and the transfer ends.
· For transfer modes E and F, set this register to number of burst
transfers. The register decrements by 1 every time one byte
is transfered. When the count reaches x'00', an ATC1
interrupt occurs and the transfer ends.
transfers. The register decrements by 1 every time one byte
is transfered. When the count reaches x'00', an ATC1
interrupt occurs and the transfer ends.
0
1
2
4
5
6
7
3