Panasonic MN101C77C User Manual

Chapter 2 CPU Basics

II - 2

Overview

2-1

Overview

The MN101C CPU has a flexible optimized hardware configuration. It is a high speed CPU with a simple

and efficient instruction set. Specific features are as follows:

Table 2-1-1 Basic Specifications

1. Minimized code sizes with instruction lengths based on 4-bit increments

The series keeps code sizes down by adopting a basic instruction length of one byte and variable

instruction lengths based on 4-bit increments.

2. Minimum execution instruction time is one system clock cycle.

3. Minimized register set that simplifies the architecture and supports C language

The instruction set has been determined, depending on the size and capacity of hardware, after

an analysis of embedded application programing code and creation code by C language compiler.

Therefore, the set is simple instruction using the minimal register set required for C language

compiler.

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"MN101C LSI User's Manual" (Architecture Instructions) ]

Data : 8-bit x 4

Address : 16-bit x 2

PC : 19-bit

PSW : 8-bit

SP : 16-bit

Number of instructions

Addressing modes

Basic portion : 1 byte (min.)

Extended portion : 0.5-byte x n

Instruction execution

Min. 1 cycle

Inter-register operation

Min. 2 cycles

Load / store

Min. 2 cycles

Conditional branch

2 to 3 cycles

Pipeline

3-stage (instruction fetch, decode, execution)

Address space

256 KB (max. 64 KB for data)

Address

18-bit (max.)

Data

8-bit

Minimum bus cycle

1 system clock cycle

Interrupt

Vector interrupt

3 interrupt levels

STOP mode

HALT mode

Low-power
dissipation mode

Six registers

Other

Instruction length

Structure

Instructions

Basic performance

External bus

Load / store architecture