Intel N450 AU80610004653AA User Manual

22

Datasheet

LA_DATAP_[2:0]

Differential data output - positive

O

LVDS

LA_DATAN_[2:0]

Differential data output - negative

O

LVDS

LA_CLKP

Differential clock output - positive

O

LVDS

LA_CLKN

Differential clock output - negative

O

LVDS

LIBG

LVDS Reference Current. Need 2.37-KOhm pull-
down resistor

I/O

Ref

LVBG

Reserved. No connect.

O

Analog

LVREFH

Reserved. Can be connected to V

SS

 or left as No 

Connect.

I

Ref

LVREFL

Reserved. Can be connected to V

SS

 or left as No 

Connect.

I

Ref

LVDD_EN

LVDS Panel Power Enable: Panel power control 
enable control.

O

HVCMOS

LBKLT_EN

LVDS Backlight Enable: Panel backlight enable 
control.

O

HVCMOS

LBKLT_CTL

Panel Backlight Brightness Control: Panel 
brightness control.
The accuracy of the PWM duty cycle of LBKLT_CTL 
signal for any given value will be within ±20 ns.

O

HVCMOS

LCTLA_CLK

I2C based control signal (Clock) for External SSC 
clock chip control - optional

I/O

COD

LCTLB_DATA

I2C based control signal (Data) for External SSC 
clock chip control - optional

I/O

COD

LDDC_CLK

EDID support for flat panel display

I/O

COD

LDDC_DATA

EDID support for flat panel display

I/O

COD

TCK

TCK (Test Clock) provides the clock input for the 
processor Test Bus (also known as the Test Access Port).

I

TAP

OD

TDI

TDI (Test Data In) transfers serial test data into the 
processor. TDI provides the serial input needed for JTAG 
specification support.

I

TAP

OD