Intel N450 AU80610004653AA User Manual

Datasheet

27

While leveraging the Just-in-Time Scheduling and Command Overlap enhancements, 
the IMC continuously monitors pending requests to system memory for the best use of 
bandwidth and reduction of latency. If there are multiple requests to the same open 
page, these requests would be launched in a back to back manner to make optimum 
use of the open memory page. This ability to reorder requests on the fly allows the IMC 
to further reduce latency and increase bandwidth efficiency.

Processor requests for memory reads usually are weighted more heavily than writes to
memory to avoid cases of starving the processor of data to process while the writes are 
issued to system memory. Instead of having writes issued to a pending queue to be 
flushed to memory when certain watermarks are reached, which could starve the 
processor of data while it waits for the write flush to finish, the IMC monitors system 
memory requests and issues pending write requests to memory at times when they will 
not impact memory read requests. This allows for an almost continuous flow of data to 
the processor for processing.

Every supported SO-DIMM has two differential clock pairs. There are total of four clock 
pairs driven directly by the processor to two SO-DIMMs.