Intel N450 AU80610004653AA User Manual
Product codes
AU80610004653AA
Datasheet
35
Functional Description
3.2.6
VESA/VGA Mode
VESA/VGA mode provides compatibility for pre-existing software that set the display
mode using the VGA CRTC registers. Timings are generated based on the VGA register
values and the timing generator registers are not used.
mode using the VGA CRTC registers. Timings are generated based on the VGA register
values and the timing generator registers are not used.
3.2.6.1
DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between the
host system and display. Both configuration and control information can be exchanged
allowing plug-and-play systems to be realized. Support for DDC 1 and DDC 2 is
implemented. The GPU uses the CRT_DDC_CLK and CRT_DDC_DATA signals to
communicate with the analog monitor. The GPU will generate these signals at 3.3V.
External pull-up resistors and level shifting circuitry should be implemented on the
board.
host system and display. Both configuration and control information can be exchanged
allowing plug-and-play systems to be realized. Support for DDC 1 and DDC 2 is
implemented. The GPU uses the CRT_DDC_CLK and CRT_DDC_DATA signals to
communicate with the analog monitor. The GPU will generate these signals at 3.3V.
External pull-up resistors and level shifting circuitry should be implemented on the
board.
The GPU implements a hardware GMBus controller that can be used to control these
signals allowing for transactions speeds up to 100 kHz.
signals allowing for transactions speeds up to 100 kHz.
3.2.7
Multiple Display Configurations
Since the GPU has two display ports available for its two pipes, it can support up to two
different images on different display devices. The GPU integrated in this processor
supports two display modes: Dual Display Clone and Extended Desktop (LVDS + VGA).
different images on different display devices. The GPU integrated in this processor
supports two display modes: Dual Display Clone and Extended Desktop (LVDS + VGA).
3.3
Thermal Sensor
There are several registers that need to be configured to support the uncore thermal
sensor functionality and SMI# generation. Customers must enable the Catastrophic
Trip Point as protection for the processor. If the Catastrophic Trip Point is crossed, then
the processor will instantly turn off all clocks inside the device. Customers may
optionally enable the Hot Trip Point to generate SMI#. Customers will be required to
then write their own SMI# handler in BIOS that will speed up the processor (or system)
fan to cool the part.
sensor functionality and SMI# generation. Customers must enable the Catastrophic
Trip Point as protection for the processor. If the Catastrophic Trip Point is crossed, then
the processor will instantly turn off all clocks inside the device. Customers may
optionally enable the Hot Trip Point to generate SMI#. Customers will be required to
then write their own SMI# handler in BIOS that will speed up the processor (or system)
fan to cool the part.
3.3.1
PCI Device 0, Function 0
The SMICMD register requires that a bit be set to generate an SMI# when the Hot Trip
point is crossed. The ERRSTS register can be inspected for the SMI alert.
point is crossed. The ERRSTS register can be inspected for the SMI alert.
Address
Register
Symbol
Register Name
Default
Value
Access
C8-C9
ERRST
Error Status
0000h
RWC/S, RO
CC-CDh
SMICMD
SMI Command
0000h
RO, R/W