Intel N450 AU80610004653AA User Manual

Product codes
AU80610004653AA
Page of 85
Electrical Specifications
38
Datasheet
The processor utilizes differential clocks to generate the processor core(s) and memory 
controller frequency, and other internal clocks. The processor core frequency is 
determined by multiplying the processor core ratio by 166MHz. Clock multiplying within 
the processor is provided by an internal phase locked loop (PLL), which requires a 
constant frequency input, with exceptions for Spread Spectrum Clocking (SSC). 
4.3.1
PLL Power Supply
An on-die PLL filter solution is implemented on the processor. Refer to 
DC specifications.
4.4
Voltage Identification (VID)
The processor
 
uses seven voltage identification signals, VID[6:0], to support automatic 
selection of voltages. 
 specifies the voltage level corresponding to the state 
of VID[6:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low 
voltage level. If the processor is not soldered on board (VID[6:0] = 1111111), or the 
voltage regulation circuit cannot supply the voltage that is requested, the voltage 
regulator must disable itself.
VID signals are CMOS push/pull drivers. Refer to 
 for the DC specifications 
for these signals. Individual processor VID values may be set during manufacturing so 
that two devices at the same core frequency may have different VID settings. 
The VR utilized must be capable of regulating its output to the value defined by the VID 
values issued. DC specifications are included in 
Table 4-19.Voltage Identification Definition
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCC (V)
0
0
1
1
0
0
0
1.2000
0
0
1
1
0
0
1
1.1875
0
0
1
1
0
1
0
1.1750
0
0
1
1
0
1
1
1.1625
0
0
1
1
1
0
0
1.1500
0
0
1
1
1
0
1
1.1375
0
0
1
1
1
1
0
1.1250
0
0
1
1
1
1
1
1.1125
0
1
0
0
0
0
0
1.1000
0
1
0
0
0
0
1
1.0875
0
1
0
0
0
1
0
1.0750
0
1
0
0
0
1
1
1.0625
0
1
0
0
1
0
0
1.0500
0
1
0
0
1
0
1
1.0375
0
1
0
0
1
1
0
1.0250
0
1
0
0
1
1
1
1.0125